公开(公告)号：US06335494B1

公开(公告)日：2002-01-01

申请号：US09602911

申请日：2000-06-23

申请人： Roger P. Gregor ,  James P. Libous

发明人： Roger P. Gregor ,  James P. Libous

IPC分类号： H01R1204

CPC分类号： H05K1/0216 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0262 ,  H05K2201/093 ,  H05K2201/09663 ,  H01L2924/00

摘要： Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while via numbers can be increased to reduce self-inductance of the structure. Transmission lines formed by conductors in the signal layers are referenced to the correct power supply and return/image currents are made of similar path length and substantially symmetrical for both positive- and negative-going signal transitions. These effects reduce delta-I noise to levels which preserve good signal-to-noise ratios to current and foreseeable reduced signal levels.

摘要翻译： 形成配电网络的多层连接结构的功率层被分割以适应在每个功率层中连接到其上的一个或多个芯片的所有必要电压。 通过这样做，并且通过长度的这种分割允许的重新布置过孔减小，同时可以增加数字以减少结构的自感。 由信号层中的导体形成的传输线参考正确的电源，并且返回/图像电流由相似的路径长度构成，对于正向和负向信号转换都是基本对称的。 这些效应可以将Delta-I噪声降低到与当前和可预见的降低的信号电平保持良好的信噪比的电平。

公开(公告)号：US6037677A

公开(公告)日：2000-03-14

申请号：US321894

申请日：1999-05-28

申请人： Robert A. Gottschall ,  Roger P. Gregor ,  James P. Libous

发明人： Robert A. Gottschall ,  Roger P. Gregor ,  James P. Libous

IPC分类号： H01L23/498 ,  H02J1/00

CPC分类号： H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T307/50

摘要： A connection array for a chip provides a substantial increase in numbers of signal connection locations and a power distribution arrangement of improved robustness and noise immunity while accommodating multiple power supply voltages by providing pairs of sub-arrays aligned with chip edges and signal connection locations formed in columns orthogonal to a chip edge or segment of the chip perimeter. Signal connections in a column are spaced at a first pitch and columns of signal connections are spaced at a second pitch. Power connections corresponding to different power supply voltages are provided between columns of signal connections and along rows which are centered between rows of signal connections generally parallel to an edge of a chip. Power distribution layers may be formed as a mesh which extends in under the chip in alignment with power connections to the chip and beyond the perimeter of the chip, as well to provide multiple low-impedance power delivery paths to improve noise immunity. The connection pattern allows fewer layers of redistribution wiring to be used to escape the chip, reducing overall product cost. Thus improvements in functionality and performance can be supported at reduced cost, particularly for custom designed application specific integrated circuits.

摘要翻译： 用于芯片的连接阵列通过提供与芯片边缘对准的一对子阵列和形成在其中的信号连接位置而提供了大量增加的信号连接位置数量和功率分配布置，其具有改进的鲁棒性和抗噪声性，同时容纳多个电源电压 与芯片边缘或芯片周边的片段正交的列。 列中的信号连接以第一间距间隔开，并且信号连接列以第二间距间隔开。 对应于不同电源电压的电源连接提供在信号连接的列之间，并且沿着大体上平行于芯片的边缘的信号连接的行之间的行居中。 功率分配层可以形成为在芯片下方延伸的网格，其与芯片的功率连接对准并且超过芯片的周边，并且提供多个低阻抗功率传递路径以改善抗噪声性。 连接图案允许使用较少的再分配布线层来逸出芯片，从而降低整体产品成本。 因此，可以以降低的成本支持功能和性能的改进，特别是对于定制设计的专用集成电路。

公开(公告)号：US06584606B1

公开(公告)日：2003-06-24

申请号：US09584416

申请日：2000-06-01

申请人： Charles S. Chiu ,  James P. Libous ,  Rory D. Loughran ,  Joseph Natonio ,  Robert A. Proctor ,  Gulsun Yasar

发明人： Charles S. Chiu ,  James P. Libous ,  Rory D. Loughran ,  Joseph Natonio ,  Robert A. Proctor ,  Gulsun Yasar

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.

摘要翻译： 分析集成电路（例如ASIC）的I / O单元布局的方法包括在所选择的芯片图像上定义所提出的I / O单元布局，为电迁移，IR电压降和di / dt噪声提供一组限制规则 所选择的芯片图像，为所提出的I / O单元布局中使用的每个I / O单元类型提供特征，通过对所提出的I / O单元布局应用限制规则来检查所提出的I / O单元布局，并报告所有I / 在所提出的I / O单元布局中使用的O单元不符合所选芯片图像的限制规则。