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16 条记录 (耗时 0.041 秒)

    Fast method of I/O circuit placement and electrical rule checking
    1.
    发明授权
    Fast method of I/O circuit placement and electrical rule checking 失效
    快速的I / O电路放置方法和电气规则检查

    公开(公告)号：US06584606B1

    公开(公告)日：2003-06-24

    申请号：US09584416

    申请日：2000-06-01

    申请人： Charles S. Chiu ,  James P. Libous ,  Rory D. Loughran ,  Joseph Natonio ,  Robert A. Proctor ,  Gulsun Yasar

    发明人： Charles S. Chiu ,  James P. Libous ,  Rory D. Loughran ,  Joseph Natonio ,  Robert A. Proctor ,  Gulsun Yasar

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.

    摘要翻译： 分析集成电路（例如ASIC）的I / O单元布局的方法包括在所选择的芯片图像上定义所提出的I / O单元布局，为电迁移，IR电压降和di / dt噪声提供一组限制规则 所选择的芯片图像，为所提出的I / O单元布局中使用的每个I / O单元类型提供特征，通过对所提出的I / O单元布局应用限制规则来检查所提出的I / O单元布局，并报告所有I / 在所提出的I / O单元布局中使用的O单元不符合所选芯片图像的限制规则。

    Method for enhancing a power bus in I/O regions of an ASIC device
    2.
    发明授权
    Method for enhancing a power bus in I/O regions of an ASIC device 失效
    用于增强ASIC设备的I / O区域中的电力总线的方法

    公开(公告)号：US06598216B2

    公开(公告)日：2003-07-22

    申请号：US09924673

    申请日：2001-08-08

    申请人： Francis Chan ,  Charles S. Chiu ,  Robert Charles Cusimano ,  Donald S. Kent ,  Gulsun Yasar

    发明人： Francis Chan ,  Charles S. Chiu ,  Robert Charles Cusimano ,  Donald S. Kent ,  Gulsun Yasar

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068

    摘要： A method for enhancing power bus for I/O libraries in ASIC designs is disclosed. An I/O assignment for I/O circuits to be utilized in an ASIC design is initially generated. Each I/O circuit may obtain power from either a primary I/O power bus or a secondary I/O power bus. A determination is then made as to whether or not the I/O assignment meets certain predetermined power distribution requirements. In a determination that the I/O assignment does not meet the predetermined power bus distribution requirements, a power enhancement cell is added. The power enhancement circuit includes at least one metal line for connecting the primary I/O power bus to the secondary I/O power bus in order for the I/O assignment to meet the power bus distribution requirements.

    摘要翻译： 公开了一种用于增强ASIC设计中的I / O库的电源总线的方法。 最初生成用于ASIC设计中的I / O电路的I / O分配。 每个I / O电路可以从主I / O电源总线或辅助I / O电源总线获得电源。 然后确定I / O分配是否满足某些预定的功率分配要求。 在确定I / O分配不满足预定功率总线分配要求的情况下，增加功率增强单元。 功率增强电路包括用于将主I / O电源总线连接到辅助I / O电源总线的至少一个金属线，以便I / O分配满足电力总线分配要求。

    System and method for modeling I/O simultaneous switching noise
    3.
    发明授权
    System and method for modeling I/O simultaneous switching noise 失效
    I / O同时开关噪声建模的系统和方法

    公开(公告)号：US08510697B2

    公开(公告)日：2013-08-13

    申请号：US13448925

    申请日：2012-04-17

    申请人： Erik Breiland ,  Charles S. Chiu ,  Prince George

    发明人： Erik Breiland ,  Charles S. Chiu ,  Prince George

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

    摘要翻译： 本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响 。 一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子 芯片封装。

    Method of designing a voltage partitioned solder-bump package
    4.
    发明授权
    Method of designing a voltage partitioned solder-bump package 有权
    设计电压分隔焊料凸点封装的方法

    公开(公告)号：US06584596B2

    公开(公告)日：2003-06-24

    申请号：US09682584

    申请日：2001-09-24

    申请人： Patrick H. Buffet ,  Charles S. Chiu ,  Yu H. Sun

    发明人： Patrick H. Buffet ,  Charles S. Chiu ,  Yu H. Sun

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036 ,  G06F2217/40

    摘要： Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.

    摘要翻译： 公开了一种设计用于芯片的焊料凸块封装中的电压隔板的方法，包括：确定芯片电压岛的电流要求，芯片电压岛包括芯片功率和信号焊盘，并创建芯片电压的等效电路模型 岛; 定义封装电压岛，封装电压岛包括电源和信号封装引脚，并创建封装电压岛的等效电路模型; 分析芯片电压岛模型和封装电压岛模型组合的电气属性; 并修改封装电压岛直到电气属性是可接受的。

    METHOD FOR RAPID RETURN PATH TRACING
    5.
    发明申请
    METHOD FOR RAPID RETURN PATH TRACING 审中-公开
    快速返回路径追踪方法

    公开(公告)号：US20090094564A1

    公开(公告)日：2009-04-09

    申请号：US11866591

    申请日：2007-10-03

    申请人： Timothy W. Budell ,  Charles S. Chiu ,  David C. Reynolds ,  Eric W. Tremble

    发明人： Timothy W. Budell ,  Charles S. Chiu ,  David C. Reynolds ,  Eric W. Tremble

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method for quickly tracing minimum-length conductive return paths through an electronic structure utilizes a raster based (cellular) memory model comprising individual grids for each layer of the structure. Each grid comprises a reduced resolution N×M cell representation of the conductive structures on that layer. Cellular methodologies are then used to determine, for each signal net, the shortest return path. This information can then be used for various purposes, including determining if the return path is sufficient to ensure adequate signal integrity.

    摘要翻译： 用于快速跟踪通过电子结构的最小长度导电返回路径的方法利用基于光栅的（蜂窝）存储器模型，其包括用于结构的每个层的各个格栅。 每个网格包括该层上的导电结构的降低分辨率的N×M单元表示。 然后使用蜂窝方法来确定每个信号网络的最短返回路径。 然后，该信息可用于各种目的，包括确定返回路径是否足以确保足够的信号完整性。

    Apparatus and method to reduce signal cross-talk
    6.
    发明授权
    Apparatus and method to reduce signal cross-talk 失效
    降低信号串扰的装置和方法

    公开(公告)号：US07038319B2

    公开(公告)日：2006-05-02

    申请号：US10644372

    申请日：2003-08-20

    申请人： Patrick H. Buffet ,  Charles S. Chiu ,  Jon D. Garlett ,  Louis L. Hsu ,  Brian J. Schuh

    发明人： Patrick H. Buffet ,  Charles S. Chiu ,  Jon D. Garlett ,  Louis L. Hsu ,  Brian J. Schuh

    IPC分类号： H01L23/48

    CPC分类号： H01L23/642 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/05599

    摘要： A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.

    摘要翻译： 公开了一种在载体层中的相邻信号之间的串扰减小的半导体芯片封装。 用于承载第一信号的第一对导体提供在载体的层中。 用于承载第二信号的第二对导体被提供为邻近层中的第一对导体，其中第一和第二对导体被配置为使得第一和第二对导体之间的串扰基本上最小化， 而不会增加包装的尺寸。 第一对导体的高度比第二对导体短。 或者，第一和第二对导体被配置成使得它们彼此均匀地影响。 芯片封装因此减少串扰，而不会影响封装中互连的密度，或导致封装尺寸的增加。

    EARLY DECOUPLING CAPACITOR OPTIMIZATION METHOD FOR HIERARCHICAL CIRCUIT DESIGN
    7.
    发明申请
    EARLY DECOUPLING CAPACITOR OPTIMIZATION METHOD FOR HIERARCHICAL CIRCUIT DESIGN 失效
    用于分层电路设计的早期解耦电容优化方法

    公开(公告)号：US20130054202A1

    公开(公告)日：2013-02-28

    申请号：US13219813

    申请日：2011-08-29

    申请人： Kurt A. Carlsen ,  Charles S. Chiu ,  Umberto Garofano ,  Ze Gui Pang ,  Eric W. Tremble ,  David Toub ,  Ivan L. Wemple

    发明人： Kurt A. Carlsen ,  Charles S. Chiu ,  Umberto Garofano ,  Ze Gui Pang ,  Eric W. Tremble ,  David Toub ,  Ivan L. Wemple

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5063 ,  G06F2217/78 ,  G06F2217/82

    摘要： Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.

    摘要翻译： 方法，系统，计算机程序等为集成电路的一个区域确定所需数量的去耦电容器和去耦电容器的近似位置。 该区域的切换元件被输入到在计算机化设备上运行的仿真程序中。 此外，该区域的配电模型被输入到模拟程序中，并且将电源电压压缩目标输入到模拟程序中。 当所有开关元件同时切换时，这些方法，系统等产生满足压缩目标所需的去耦电容器的数量。 对于每个开关元件，方法，系统等产生特定数量的去耦电容器，以便在仅元件切换时满足压缩，将特定数量的一部分计算为上限，分配总数的分数 的去耦电容器到每个开关电路元件，并将去耦电容器总数的一部分放置在电气附近的元件上。

    System and method for modeling I/O simultaneous switching noise
    10.
    发明授权
    System and method for modeling I/O simultaneous switching noise 有权
    I / O同时开关噪声建模的系统和方法

    公开(公告)号：US08234611B2

    公开(公告)日：2012-07-31

    申请号：US12166550

    申请日：2008-07-02

    申请人： Erik Breiland ,  Charles S. Chiu ,  Prince George

    发明人： Erik Breiland ,  Charles S. Chiu ,  Prince George

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

    摘要翻译： 本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响 。 一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子 芯片封装。