公开(公告)号：US07256636B2

公开(公告)日：2007-08-14

申请号：US11240231

申请日：2005-09-30

申请人： Rohit Kumar ,  Anand Daga ,  Sanjay Sethi

发明人： Rohit Kumar ,  Anand Daga ,  Sanjay Sethi

IPC分类号： H03H11/26

CPC分类号： H03L7/0812

摘要： A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).

公开(公告)号：US20070075757A1

公开(公告)日：2007-04-05

申请号：US11240231

申请日：2005-09-30

申请人： Rohit Kumar ,  Anand Daga ,  Sanjay Sethi

发明人： Rohit Kumar ,  Anand Daga ,  Sanjay Sethi

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).

摘要翻译： 电压控制延时线（VCDL）。 VCDL包括一个或多个单元。 一个或多个单元中的每个单元包括两个或更多个输入和输出。 一个或多个单元中的每一个被配置为提供延迟以及内插函数和多路复用器功能。 VCDL可用于在延迟锁定环（DLL）中提供延迟。

公开(公告)号：US07271634B1

公开(公告)日：2007-09-18

申请号：US11286454

申请日：2005-11-23

申请人： Anand Daga ,  Sanjay Sethi ,  Philip E. Madrid

发明人： Anand Daga ,  Sanjay Sethi ,  Philip E. Madrid

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/093

摘要： A delay-locked loop (DLL) has a counter that is incremented or decremented by the loop in the process of achieving lock. The counter value is converted using an digital to analog converter (DAC) to an analog voltage that controls the delay through the delay line. During faster lock modes, the loop increments/decrements intermediate bits of the counter (with the bits less significant being held at a constant value, e.g., 0) to provide a coarse lock, rather than incrementing/decrementing the least significant bit of the counter. After coarse lock is achieved, a better lock is then achieved by incrementing/decrementing the counter using a smaller increment, i.e., a less significant bit is updated, until finally, the LSB is utilized to achieve fine lock. Utilizing the coarse lock first, and then one or more finer locks, allows the lock to be achieved more quickly.

摘要翻译： 延迟锁定循环（DLL）具有在实现锁定的过程中由循环递增或递减的计数器。 使用数模转换器（DAC）将计数器值转换为控制延迟线延迟的模拟电压。 在更快的锁定模式期间，循环递增/递减计数器的中间位（位不太显着被保持在恒定值，例如0），以提供粗略锁定，而不是递增/递减计数器的最低有效位 。 在实现粗略锁定之后，通过使用较小的增量递增/递减计数器来实现更好的锁定，即，较不重要的位被更新，直到最后使用LSB来实现精细锁定。 首先使用粗锁，然后使用一个或多个更精细的锁，可以更快地实现锁定。

公开(公告)号：US08356270B2

公开(公告)日：2013-01-15

申请号：US12907316

申请日：2010-10-19

申请人： Tom Burd ,  Yuri Apanovich ,  Srinivasaraghavan Krishnamoorthy ,  Vishak Kumar Venkatraman ,  Anand Daga

发明人： Tom Burd ,  Yuri Apanovich ,  Srinivasaraghavan Krishnamoorthy ,  Vishak Kumar Venkatraman ,  Anand Daga

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F2217/82

摘要： A system and method for providing a statistical budgeting approach to modeling reliability effects such as interconnect electromigration (EM), transistor time-dependant dielectric breakdown (TDDB), hot-carrier injection effects (HCI) and bias temperature instability (BTI) is disclosed. A static analysis flow captures the effects of design topology, switching constraints, interactions between signal nets and supply rails as well as thermal gradients due to interconnect and transistor self as well as mutual heating, and was used to verify successive iterations of deep sub-micron integrated circuit designs.

摘要翻译： 公开了一种用于提供统计预算方法来建模诸如互连电迁移（EM），晶体管时间依赖介质击穿（TDDB），热载流子注入效应（HCI）和偏置温度不稳定性（BTI）的可靠性效应的系统和方法。 静态分析流程捕获设计拓扑，开关约束，信号网络和电源轨之间的相互作用以及由于互连和晶体管自身以及相互加热引起的热梯度的影响，并用于验证深亚微米的连续迭代 集成电路设计。

公开(公告)号：US20120096424A1

公开(公告)日：2012-04-19

申请号：US12907316

申请日：2010-10-19

申请人： Tom Burd ,  Yuri Apanovich ,  Srinivasaraghavan Krishnamoorthy ,  Vishak Kumar Venkatraman ,  Anand Daga

发明人： Tom Burd ,  Yuri Apanovich ,  Srinivasaraghavan Krishnamoorthy ,  Vishak Kumar Venkatraman ,  Anand Daga

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F2217/82

摘要： A system and method for providing a statistical budgeting approach to modeling reliability effects such as interconnect electromigration (EM), transistor time-dependant dielectric breakdown (TDDB), hot-carrier injection effects (HCI) and bias temperature instability (BTI) is disclosed. A static analysis flow captures the effects of design topology, switching constraints, interactions between signal nets and supply rails as well as thermal gradients due to interconnect and transistor self as well as mutual heating, and was used to verify successive iterations of deep sub-micron integrated circuit designs.

摘要翻译： 公开了一种用于提供统计预算方法来建模诸如互连电迁移（EM），晶体管时间依赖介质击穿（TDDB），热载流子注入效应（HCI）和偏置温度不稳定性（BTI）的可靠性效应的系统和方法。 静态分析流程捕获设计拓扑，开关约束，信号网络和电源轨之间的相互作用以及由于互连和晶体管自身以及相互加热引起的热梯度的影响，并用于验证深亚微米的连续迭代 集成电路设计。

公开(公告)号：US07425858B1

公开(公告)日：2008-09-16

申请号：US11327572

申请日：2006-01-06

申请人： Anand Daga

发明人： Anand Daga

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  H03L7/0812 ,  H03L7/095

摘要： A delay line is periodically configured into a delay-locked loop for calibration purposes. That is, the delay line is operated in an open loop mode during a first time period in which a signal, such as an aperiodic signal, is the input signal into the delay line. Periodically, the delay line is configured into a delay-locked loop and the delay line is recalibrated based on a periodic signal supplied to the delay-locked loop.

摘要翻译： 延迟线周期性地配置成延迟锁定环路用于校准目的。 也就是说，延迟线在其中诸如非周期性信号的信号是进入延迟线的输入信号的第一时间段期间以开环模式操作。 周期性地，延迟线被配置成延迟锁定环路，并且延迟线路基于提供给延迟锁定环路的周期信号被重新校准。