公开(公告)号：US07305586B2

公开(公告)日：2007-12-04

申请号：US10424485

申请日：2003-04-25

申请人： Richard William Doing ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  John Wesley Ward, III

发明人： Richard William Doing ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  John Wesley Ward, III

IPC分类号： G06F11/00

CPC分类号： G06F11/2236

摘要： A microprocessor includes an externally accessible port and a serial communication bus connected to the port. An execution pipeline of the processor includes a pipeline satellite circuit coupling the pipeline to the bus. The satellite enables an external agent to provide an instruction directly to the pipeline via the serial bus. A dedicated register and register satellite circuit couple the register to the communication bus. The execution pipeline can access the dedicated register during execution of the instruction. In this manner, the satellite circuits enable the external agent to access architected state. The communication bus enables access to the satellites while a system clock to the processor remains active. In one embodiment, the pipeline satellite accesses the pipeline “downstream” of the decode stage such that the set of instructions that may be “rammed” into the pipeline is not limited to the set of instructions that the decode stage can generate.

摘要翻译： 微处理器包括外部可访问端口和连接到端口的串行通信总线。 处理器的执行流水线包括将管道耦合到总线的流水线卫星电路。 该卫星使外部代理可以通过串行总线直接向管线提供指令。 专用寄存器和寄存器卫星电路将寄存器耦合到通信总线。 在执行指令期间，执行流水线可以访问专用寄存器。 以这种方式，卫星电路使外部代理能够访问架构状态。 当处理器的系统时钟保持有效时，通信总线可以访问卫星。 在一个实施例中，流水线卫星访问解码级的“下游”流水线，使得可能被“冲撞”到流水线中的指令集不限于解码级可以产生的一组指令。

公开(公告)号：US06829684B2

公开(公告)日：2004-12-07

申请号：US10175626

申请日：2002-06-20

申请人： Richard William Doing ,  Ronald Nick Kalla ,  Stephen Joseph Schwinn ,  Edward John Silha ,  Kenichi Tsuchiya

发明人： Richard William Doing ,  Ronald Nick Kalla ,  Stephen Joseph Schwinn ,  Edward John Silha ,  Kenichi Tsuchiya

IPC分类号： G06F1214

CPC分类号： G06F9/3804 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/5077 ,  G06F12/0284 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/1491

摘要： A real address range check mechanism verifies real addresses generated in a computer system which translates real addresses from effective addresses, some of the effective addresses being real addresses not requiring translation. The system has at least two operating modes. In one mode, the range checking mechanism generates an error signal responsive to detecting a real address outside a predetermined range, and in the other operating mode no error signal is generated. Preferably, the computer system's hardware resources, including real address space, is logically partitioned, partitioning being managed by an ultra-privileged process called a hypervisor. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, real address range checking error signals being disabled in the hypervisor state.

摘要翻译： 实际的地址范围检查机制验证计算机系统中产生的真实地址，其中可以从有效地址转换实际地址，一些有效地址是不需要翻译的实际地址。 系统至少有两种操作模式。 在一种模式中，范围检查机构响应于检测到超出预定范围的实际地址产生误差信号，而在其它操作模式中，不产生误差信号。 优选地，计算机系统的硬件资源（包括实际地址空间）在逻辑上被分区，由被称为管理程序的超特权进程管理分区。 优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中，虚拟机管理程序状态中的实际地址范围检查错误信号被禁用。

公开(公告)号：US06438671B1

公开(公告)日：2002-08-20

申请号：US09346206

申请日：1999-07-01

申请人： Richard William Doing ,  Ronald Nick Kalla ,  Stephen Joseph Schwinn ,  Edward John Silha ,  Kenichi Tsuchiya

发明人： Richard William Doing ,  Ronald Nick Kalla ,  Stephen Joseph Schwinn ,  Edward John Silha ,  Kenichi Tsuchiya

IPC分类号： G06F1206

CPC分类号： G06F9/3804 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/5077 ,  G06F12/0284 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/1491

摘要： A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not. In the preferred embodiment, instruction addresses from either active or dormant threads can be pre-fetched in anticipation of execution. In the preferred embodiment, the processor supports different environments which use the hypervisor, supervisor and problem states differently.

摘要翻译： 处理器支持计算机系统的逻辑分区。 逻辑分区隔离在不同处理器上执行的进程的真实地址空间以及包含处理器的硬件资源。 然而，该多线程处理器系统可以在逻辑分区中动态地重新分配包括处理器在内的硬件资源。 一个超级特权的管理程序，称为管理程序，它调节逻辑分区。 优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中。 处理器将某些生成的地址分配给其逻辑分区，优选地通过将特定寄存器中的某些高阶位与所生成的地址的较低位相连。 单独的范围检查机制同时验证这些高阶有效地址位实际上为0，并且如果它们不是，则产生错误信号。 在优选实施例中，来自主动或休眠线程的指令地址可以预期执行。 在优选实施例中，处理器支持使用管理程序，主管和问题状态不同的不同环境。

公开(公告)号：US06993640B2

公开(公告)日：2006-01-31

申请号：US10948776

申请日：2004-09-23

申请人： Richard William Doing ,  Ronald Nick Kalla ,  Stephen Joseph Schwinn ,  Edward John Silha ,  Kenichi Tsuchiya

发明人： Richard William Doing ,  Ronald Nick Kalla ,  Stephen Joseph Schwinn ,  Edward John Silha ,  Kenichi Tsuchiya

IPC分类号： G06F9/50

CPC分类号： G06F9/3804 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/5077 ,  G06F12/0284 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/1491

摘要： A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.

摘要翻译： 处理器支持包括计算机系统的真实地址空间的硬件资源的逻辑分区。 一个超级特权的管理程序称为虚拟机管理程序，可以调节逻辑分区，并可以动态重新分配资源。 优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中，并且仅在某些预定义事件发生时能够进入管理程序状态。 逻辑分区标识符存储在处理器寄存器中，并且只有处于管理程序状态时才能被处理器改变。 某些总线通信包含逻辑分区标识符标签，如果标记与其寄存器中的自己的逻辑分区标识符不匹配，则处理器忽略此类通信。

公开(公告)号：US6161166A

公开(公告)日：2000-12-12

申请号：US266133

申请日：1999-03-10

申请人： Richard William Doing ,  Ronald Nick Kalla ,  Stephen Joseph Schwinn

发明人： Richard William Doing ,  Ronald Nick Kalla ,  Stephen Joseph Schwinn

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0859 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/1036 ,  G06F12/1054

摘要： A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory containing real page numbers of the corresponding cache lines. A separate line fill sequencer exists for each thread. Preferably, the I-cache is N-way set associative, where N is the number of threads, and includes an effective-to-real address table (ERAT), containing pairs of effective and real page numbers. ERAT entries are accessed by hashing the effective address. The ERAT entry is then compared with the effective address of the desired instruction to verify an ERAT hit. The corresponding real page number is compared with a real page number in the directory array to verify a cache hit. Preferably, the line fill sequencer operates in response to a cache miss, where there is an ERAT hit. In this case, the full real address of the desired instruction can be constructed from the effective address and the ERAT, making it unnecessary to access slower address translation mechanisms for main memory. Because there is a separate line fill sequencer for each thread, threads are independently able to satisfy cache fill requests without waiting for each other. Additionally, because the I-cache index contains real page numbers, cache coherency is simplified. Furthermore, the ERAT avoids the need in many cases to access slower memory translation mechanisms. Finally, the n-way associative nature of the cache reduces thread contention.

摘要翻译： 多线程处理器包括由所有线程共享的一级指令高速缓存。 使用指令单元生成有效地址访问I缓存，I缓存目录包含相应缓存行的实际页码。 每个线程都存在单独的行填充序列发生器。 优选地，I缓存是N路组关联，其中N是线程数，并且包括有效到真实地址表（ERAT），其包含有效和真实页码对。 通过散列有效地址来访问ERAT条目。 然后将ERAT条目与所需指令的有效地址进行比较，以验证ERAT命中。 将相应的实际页码与目录数组中的真实页码进行比较，以验证缓存命中。 优选地，线填充定序器响应于存在ERAT命中的高速缓存未命中而操作。 在这种情况下，可以通过有效地址和ERAT构建所需指令的完整实际地址，从而无需访问较慢的主存储器的地址转换机制。 因为每个线程都有一个单独的行填充顺控程序，线程可以独立地满足缓存填充请求，而无需等待彼此。 另外，因为I缓存索引包含真实的页码，所以缓存一致性被简化。 此外，ERAT避免了在许多情况下访问较慢内存转换机制的需要。 最后，缓存的n路关联属性减少线程争用。

公开(公告)号：US20080276071A1

公开(公告)日：2008-11-06

申请号：US12176386

申请日：2008-07-20

申请人： Richard William Doing ,  Brett Olsson ,  Kenichi Tsuchiya

发明人： Richard William Doing ,  Brett Olsson ,  Kenichi Tsuchiya

IPC分类号： G06F9/312

CPC分类号： G06F9/3804 ,  G06F9/3844

摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

摘要翻译： 一种用于减少预测的分支指令的目标指令的获取时间的方法和处理器。 缓冲器中的每个条目（这里称为“分支目标缓冲器”）可以存储预测的分支指令的地址和从预测的分支指令的目标地址开始的指令。 当从指令高速缓存中取出指令时，使用获取的指令的特定位来对分支目标缓冲器中的特定条目进行索引。 将索引条目中的分支指令的地址与从指令高速缓存获取的指令的地址进行比较。 如果有匹配，则从该分支指令的目标地址开始的指令直接在分支指令的后面进行调度。 以这种方式，减少预测的分支指令的目标指令的获取时间。

公开(公告)号：US20100257340A1

公开(公告)日：2010-10-07

申请号：US12417798

申请日：2009-04-03

申请人： Richard William Doing ,  Kevin Neal Magil ,  Balaram Sinharoy ,  Jeffrey R. Summers ,  James A. Van Norstrand, JR.

发明人： Richard William Doing ,  Kevin Neal Magil ,  Balaram Sinharoy ,  Jeffrey R. Summers ,  James A. Van Norstrand, JR.

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3853

摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.

摘要翻译： 公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。 在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。 组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。 在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。 在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。

公开(公告)号：US08479184B2

公开(公告)日：2013-07-02

申请号：US12861955

申请日：2010-08-24

申请人： Richard William Doing ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Mauricio Jose Serrano ,  Zhong Liang Wang

发明人： Richard William Doing ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Mauricio Jose Serrano ,  Zhong Liang Wang

IPC分类号： G06F9/45

CPC分类号： G06F11/3466 ,  G06F8/443 ,  G06F9/30076 ,  G06F2201/865

摘要： An information handling system includes a memory, a processor, and an instruction tracking unit. The processor executes program code and, while the program code executes, the instruction tracking unit decodes a multi-purpose no-op instruction within the program code. In turn, the instruction tracking unit sends an interrupt to the processor, which invokes a profiling module to collect and store profiling data in a profiling buffer.

摘要翻译： 信息处理系统包括存储器，处理器和指令跟踪单元。 处理器执行程序代码，并且在程序代码执行时，指令跟踪单元对程序代码内的多用途无操作指令进行解码。 反过来，指令跟踪单元向处理器发送中断，该处理器调用分析模块以在分析缓冲器中收集和存储分析数据。

公开(公告)号：US08127115B2

公开(公告)日：2012-02-28

申请号：US12417798

申请日：2009-04-03

申请人： Richard William Doing ,  Kevin Neal Magil ,  Balaram Sinharoy ,  Jeffrey R. Summers ,  James Albert Van Norstrand, Jr.

发明人： Richard William Doing ,  Kevin Neal Magil ,  Balaram Sinharoy ,  Jeffrey R. Summers ,  James Albert Van Norstrand, Jr.

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3853

摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.

摘要翻译： 公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。 在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。 组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。 在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。 在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。

公开(公告)号：US08015565B2

公开(公告)日：2011-09-06

申请号：US11284257

申请日：2005-11-21

申请人： Richard William Doing ,  John R. Patty ,  Steven Robert Testa ,  Thuong Quang Truong

发明人： Richard William Doing ,  John R. Patty ,  Steven Robert Testa ,  Thuong Quang Truong

IPC分类号： G06F9/46

CPC分类号： G06F9/524

摘要： A method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a round robin selection mechanism is used for further requests. A livelock-preventing selection mechanism includes a pair of linear feedback shift registers (LFSRs), each LFSR for generating pseudo random values.

摘要翻译： 提供了一种用于在多处理器（MP）系统中防止处理器选择负载请求中的活动锁定的方法和装置。 在随机的情况下，改变选择机制以首先保持所有请求，然后进行随机选择。 然后轮询选择机制用于进一步的请求。 防锁选择机构包括一对线性反馈移位寄存器（LFSR），每个LFSR用于产生伪随机值。