Method for Forming Single-Level Electrically Erasable and Programmable Read Only Memory Operated in Environment with High/Low-Voltage
    1.
    发明申请
    Method for Forming Single-Level Electrically Erasable and Programmable Read Only Memory Operated in Environment with High/Low-Voltage 审中-公开
    在高/低电压环境下形成单级电可擦除可编程只读存储器的方法

    公开(公告)号:US20100240181A1

    公开(公告)日:2010-09-23

    申请号:US12789364

    申请日:2010-05-27

    IPC分类号: H01L21/336

    摘要: First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

    摘要翻译: 首先,提供半导体衬底,然后在其中形成具有第一导电性的第一/第二阱,以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件,其中 第一井和第二井用于分离高压装置,第一井的深度与第二井相同。 此外,单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上,并且形成单级EEPROM的浮置栅极的控制栅极 位于单电平EEPROM的浮置栅极的第二部分下方的第三阱中,其中高电压装置可以在大约18V的相对电场中操作,例如-6V〜12V,-12V〜6V,-9V 〜9V等