公开(公告)号：US20100240181A1

公开(公告)日：2010-09-23

申请号：US12789364

申请日：2010-05-27

申请人： Rong-Ching CHEN ,  Ching-Chun HUANG ,  Jy-Hwang LIN

发明人： Rong-Ching CHEN ,  Ching-Chun HUANG ,  Jy-Hwang LIN

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/981

摘要： First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

摘要翻译： 首先，提供半导体衬底，然后在其中形成具有第一导电性的第一/第二阱，以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件，其中 第一井和第二井用于分离高压装置，第一井的深度与第二井相同。 此外，单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上，并且形成单级EEPROM的浮置栅极的控制栅极 位于单电平EEPROM的浮置栅极的第二部分下方的第三阱中，其中高电压装置可以在大约18V的相对电场中操作，例如-6V〜12V，-12V〜6V，-9V 〜9V等

公开(公告)号：US07091079B2

公开(公告)日：2006-08-15

申请号：US10904455

申请日：2004-11-11

申请人： Jung-Ching Chen ,  Jy-Hwang Lin

发明人： Jung-Ching Chen ,  Jy-Hwang Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

摘要： The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a plurality of n-wells and a plurality of p-wells are in the HV region, the MV region, and the LV region. Following that, a plurality of HV devices are formed in the HV region, a plurality of MV devices are formed in the MV region, and a plurality of LV devices are formed in the LV region.

摘要翻译： 本发明提供一种形成具有不同工作电压的器件的方法。 首先，提供具有HV区域，MV区域和LV区域的基板。 然后，在衬底中形成至少包围LV区域和MV区域的深阱。 之后，多个n阱和多个p阱位于HV区域，MV区域和LV区域中。 接着，在HV区域形成多个HV器件，在MV区域形成多个MV器件，在LV区域形成多个LV器件。

公开(公告)号：US20060099753A1

公开(公告)日：2006-05-11

申请号：US10904455

申请日：2004-11-11

申请人： Jung-Ching CHEN ,  Jy-Hwang Lin

发明人： Jung-Ching CHEN ,  Jy-Hwang Lin

IPC分类号： H01L21/8234

CPC分类号： H01L21/823814 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

摘要： The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a plurality of n-wells and a plurality of p-wells are in the HV region, the MV region, and the LV region. Following that, a plurality of HV devices are formed in the HV region, a plurality of MV devices are formed in the MV region, and a plurality of LV devices are formed in the LV region.

摘要翻译： 本发明提供一种形成具有不同工作电压的器件的方法。 首先，提供具有HV区域，MV区域和LV区域的基板。 然后，在衬底中形成至少包围LV区域和MV区域的深阱。 之后，多个n阱和多个p阱位于HV区域，MV区域和LV区域中。 接着，在HV区域形成多个HV器件，在MV区域形成多个MV器件，在LV区域形成多个LV器件。

公开(公告)号：US6165895A

公开(公告)日：2000-12-26

申请号：US344865

申请日：1999-06-28

申请人： Jy-Hwang Lin

发明人： Jy-Hwang Lin

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/0276 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897

摘要： A method of fabricating an interconnect is described in which a conductive layer, an anti-reflection layer and a cover layer are sequentially formed on the substrate to form a conductive plug with its bottom situated in the anti-reflection layer. The cover layer and a portion of the anti-reflection layer and the conductive layer are remove to form an opening exposing the substrate and to define the conductive lining structures. A conformal polysilicon oxide layer is formed on the substrate and a first dielectric layer is also formed, filling the opening. A conformal isolation layer is then formed on the substrate, followed by forming a second dielectric layer covering the entire substrate. A planarization procedure is further conducted to expose the conductive plug.

摘要翻译： 描述了制造互连的方法，其中在衬底上依次形成导电层，抗反射层和覆盖层，以形成其底部位于抗反射层中的导电插塞。 去除覆盖层和防反射层和导电层的一部分以形成露出衬底并限定导电衬里结构的开口。 在基板上形成保形多晶硅氧化物层，并且还形成填充开口的第一介电层。 然后在衬底上形成保形隔离层，随后形成覆盖整个衬底的第二介电层。 进一步进行平面化处理以暴露导电插塞。

公开(公告)号：US07256092B2

公开(公告)日：2007-08-14

申请号：US10710616

申请日：2004-07-25

申请人： Jung-Ching Chen ,  Jy-Hwang Lin ,  Sheng-Hsiung Yang ,  Jim Su

发明人： Jung-Ching Chen ,  Jy-Hwang Lin ,  Sheng-Hsiung Yang ,  Jim Su

IPC分类号： H01L21/8232

CPC分类号： H01L29/1083 ,  H01L21/2652 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/7833

摘要： A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.

摘要翻译： 提供了与低压MOS工艺完全兼容的高压半导体MOS工艺。 在定义有源区之前，将高压N / P阱注入到衬底中。 在形成场氧化物层之后形成通道停止掺杂区域，从而避免沟道停止掺杂区域的横向扩散。 此外，用于激活高压器件区域中的等级掺杂区域和高压器件的栅极氧化物生长的等级驱入工艺同时进行。

公开(公告)号：US6150916A

公开(公告)日：2000-11-21

申请号：US149929

申请日：1998-09-09

申请人： Jy-Hwang Lin ,  Tsan-Wen Liu

发明人： Jy-Hwang Lin ,  Tsan-Wen Liu

IPC分类号： H01L23/525 ,  H01L27/108 ,  H01H37/36 ,  H01L27/10 ,  H01L27/115

CPC分类号： H01L23/5258 ,  H01L27/10897 ,  H01L2924/0002

摘要： An architecture of poly fuses includes a number of fuses, a dielectric layer, a sheet-like etching stop layer, and a passivation layer, wherein the sheet-like etching stop layer further includes a number of slices, and wherein each of the slices corresponds to one of the fuses underneath. The architecture of poly fuses according to the invention reduces the energy dispersion during the defective recovering process, and improves the recovery rate for defective memory cells.

摘要翻译： 多熔丝的结构包括多个保险丝，电介质层，片状蚀刻停止层和钝化层，其中片状蚀刻停止层还包括多个片，并且其中每个片对应于 到下面的保险丝之一。 根据本发明的多熔丝的结构降低了在有缺陷的恢复过程中的能量分散，并提高了有缺陷的存储单元的恢复率。

公开(公告)号：US20070063349A1

公开(公告)日：2007-03-22

申请号：US11231264

申请日：2005-09-19

申请人： Tsui-Lien Kao ,  Huei-Ju Tsai ,  Shyan-Yhu Wang ,  Jy-Hwang Lin

发明人： Tsui-Lien Kao ,  Huei-Ju Tsai ,  Shyan-Yhu Wang ,  Jy-Hwang Lin

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76829 ,  H01L21/76819

摘要： The invention is directed to a method for manufacturing an interconnect structure suitable for a substrate having a semiconductor device formed thereon, wherein the semiconductor device possesses a metal silicide layer predetermined as an electrically connecting region. The method comprises steps of forming a conformal adhesion layer over the substrate, forming a dielectric layer on the conformal adhesion layer and then performing a chemical mechanical polishing process to planarize the dielectric layer. Further, an opening penetrating through the dielectric layer and the conformal adhesion layer is formed, wherein the opening exposes a portion of the metal silicide layer. A conductive plug is formed in the opening.

摘要翻译： 本发明涉及一种制造适合于其上形成有半导体器件的衬底的互连结构的方法，其中半导体器件具有预定为电连接区域的金属硅化物层。 该方法包括以下步骤：在衬底上形成共形粘附层，在保形粘合层上形成电介质层，然后进行化学机械抛光工艺以平坦化介电层。 此外，形成贯穿介电层和共形粘附层的开口，其中开口露出金属硅化物层的一部分。 在开口中形成导电塞。

公开(公告)号：US07005339B2

公开(公告)日：2006-02-28

申请号：US10707444

申请日：2003-12-15

申请人： Ching-Chun Huang ,  Ming-Hsien Huang ,  Rong-Ching Chen ,  Jy-Hwang Lin

发明人： Ching-Chun Huang ,  Ming-Hsien Huang ,  Rong-Ching Chen ,  Jy-Hwang Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/76229 ,  H01L21/823418 ,  H01L21/823456

摘要： The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.

摘要翻译： 本发明提供一种将至少一个高电压金属氧化物半导体器件和至少一个亚微米金属氧化物半导体器件集成在衬底上的方法。 该方法包括：提供衬底，在衬底的表面上形成具有不同深度的多个浅沟槽，以及形成填充浅沟槽的多个氧化硅层，并且每个氧化硅层的顶部处于 蘑菇的形状。

公开(公告)号：US06900097B2

公开(公告)日：2005-05-31

申请号：US10435018

申请日：2003-05-12

申请人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

发明人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/981

摘要： First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

摘要翻译： 首先，提供半导体衬底，然后在其中形成具有第一导电性的第一/第二阱，以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件，其中 第一井和第二井用于分离高压装置，第一井的深度与第二井相同。 此外，单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上，并且形成单级EEPROM的浮置栅极的控制栅极 在位于单电平EEPROM的浮置栅极的第二部分的第三阱中，其中高压器件可以在大约18V的相对电场中操作，例如-6V〜12V，-12V〜6V，-9V 〜9V等

公开(公告)号：US06462390B1

公开(公告)日：2002-10-08

申请号：US09672234

申请日：2000-09-27

申请人： Ming-Shing Chen ,  Shu-Jen Chen ,  Jy-Hwang Lin ,  Kuen-Syh Tseng

发明人： Ming-Shing Chen ,  Shu-Jen Chen ,  Jy-Hwang Lin ,  Kuen-Syh Tseng

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28044 ,  H01L29/4933

摘要： A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable to a self-aligned silicide (salicide) process, so that a sheet resistance of the salicide layer on conductive regions of the gate transistor is significantly reduced. The stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no cobalt oxide is formed when RTP is performed. Without formation of the cobalt oxide, the salicide process is free from the bridging issue and the filament issue.

摘要翻译： 公开了具有钴层，阻挡层和填充层的多层覆盖层，其中阻挡层将钴层与填料层隔离。 多层覆盖层形成在栅极晶体管上并且可应用于自对准硅化物（自对准硅化物）工艺，使得栅极晶体管的导电区域上的自对准硅化物层的薄层电阻显着降低。 填充层进一步防止氧化物或水分进入自对准硅化物层，因此在进行RTP时不会形成氧化钴。 不形成氧化钴，自对准硅化物工艺没有桥接问题和灯丝问题。