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1.发明授权Method and apparatus for optimizing the functioning of DRAM memory elements 失效用于优化DRAM存储器元件的功能的方法和装置公开(公告)号：US07072233B2
公开(公告)日：2006-07-04
申请号：US10850817
申请日：2004-05-21
CPC分类号： G11C29/028 , G11C7/1045 , G11C11/401 , G11C11/4076 , G11C29/50 , G11C29/50012
摘要： In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration. Then information on the modified default time duration or on the ascertained real time duration are stored in the memory element during the test operation mode, wherein the second operation is executed offset by the modified default time duration after the execution instant of the first operation during the normal operation mode.
摘要翻译： 在用于修改第二操作的执行时刻和先前在存储元件中执行的第一操作的较早执行时刻之间的默认持续时间的方法中，其中该存储元件可在测试操作模式和正常操作模式下操作， 首先，在测试操作模式期间确定和提供存储器元件中的实时持续时间，其中选择实时持续时间，使得当使用第一时钟的执行时刻之间的实时持续时间时，存储器元件的性能参数 并且第二操作改进了使用第一操作和第二操作的执行时刻之间的默认持续时间的情况。 然后，在测试操作模式期间，在实时持续时间的方向上改变默认持续时间，以获得修改的默认持续时间。 然后，在测试操作模式期间将关于修改的默认持续时间或所确定的实时持续时间的信息存储在存储器元件中，其中第二操作被执行偏移了在第一操作期间的执行时刻之后的修改的默认持续时间 正常运行模式。
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2.发明申请Method and apparatus for optimizing the functioning of DRAM memory elements 失效用于优化DRAM存储器元件的功能的方法和装置公开(公告)号：US20050002245A1
公开(公告)日：2005-01-06
申请号：US10850817
申请日：2004-05-21
IPC分类号： G11C7/10 , G11C11/4076 , G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C7/1045 , G11C11/401 , G11C11/4076 , G11C29/50 , G11C29/50012
摘要： In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration. Then information on the modified default time duration or on the ascertained real time duration are stored in the memory element during the test operation mode, wherein the second operation is executed offset by the modified default time duration after the execution instant of the first operation during the normal operation mode.
摘要翻译： 在用于修改第二操作的执行时刻和先前在存储元件中执行的第一操作的较早执行时刻之间的默认持续时间的方法中，其中该存储元件可在测试操作模式和正常操作模式下操作， 首先，在测试操作模式期间确定和提供存储器元件中的实时持续时间，其中选择实时持续时间，使得当使用第一时钟的执行时刻之间的实时持续时间时，存储器元件的性能参数 并且第二操作改进了使用第一操作和第二操作的执行时刻之间的默认持续时间的情况。 然后，在测试操作模式期间，在实时持续时间的方向上改变默认持续时间，以获得修改的默认持续时间。 然后，在测试操作模式期间将关于修改的默认持续时间或所确定的实时持续时间的信息存储在存储器元件中，其中第二操作被执行偏移了在第一操作期间的执行时刻之后的修改的默认持续时间 正常运行模式。
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3.发明授权Integrated circuit memory device responsive to word line/bit line short-circuit 失效集成电路存储器件响应于字线/位线短路公开(公告)号：US07697354B2
公开(公告)日：2010-04-13
申请号：US11755101
申请日：2007-05-30
IPC分类号： G11C29/00
CPC分类号： G11C7/12 , G11C11/4085 , G11C11/4094 , G11C29/02 , G11C29/025 , G11C29/83
摘要： An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.
摘要翻译： 集成电路存储器件包括具有相关联的字线和位线的存储器阵列。 开关装置连接在字线和选择性地将字线连接到第一电压源的第一电压源之间，并且还响应于字线和位线之间的短路。
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4.发明申请CURRENT REDUCTION WITH WORDLINE BIT LINE SHORT-CIRCUITS IN DRAMS AND DRAM DERIVATIVES 失效使用WORDLINE位线短路电流在DRAMS和DRAM衍生电路中减少电流公开(公告)号：US20080298149A1
公开(公告)日：2008-12-04
申请号：US11755101
申请日：2007-05-30
CPC分类号： G11C7/12 , G11C11/4085 , G11C11/4094 , G11C29/02 , G11C29/025 , G11C29/83
摘要： An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.
摘要翻译： 集成电路存储器件包括具有相关联的字线和位线的存储器阵列。 开关装置连接在字线和选择性地将字线连接到第一电压源的第一电压源之间，并且还响应于字线和位线之间的短路。
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