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公开(公告)号：US07385607B2
公开(公告)日：2008-06-10
申请号：US10938042
申请日：2004-09-10
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译： 公开了可扩展着色器架构。 根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。 着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。 着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。 着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。 着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。 每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。
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公开(公告)号：US07852340B2
公开(公告)日：2010-12-14
申请号：US11957358
申请日：2007-12-14
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译： 公开了可扩展着色器架构。 根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。 着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。 着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。 着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。 着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。 每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。
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公开(公告)号：US07821520B1
公开(公告)日：2010-10-26
申请号：US11009471
申请日：2004-12-10
CPC分类号： G06T1/20
摘要： A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader processor and as a First-In First-Out (FIFO) buffer for a subsequent module. Some embodiments include automatic, programmable hardware conversion between numeric formats, for example, between floating point data and fixed point data.
摘要翻译： 一种新的，有用的和不可见的着色器处理器架构，其具有着色器寄存器文件，其既用作内部存储寄存器文件，用于在着色器处理器内临时存储数据，并作为先进先出（FIFO）缓冲器，用于后续 模块。 一些实施例包括数字格式之间的自动，可编程硬件转换，例如在浮点数据和固定点数据之间。
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公开(公告)号：US07218291B2
公开(公告)日：2007-05-15
申请号：US10940070
申请日：2004-09-13
CPC分类号： G06T11/40 , G06T15/005 , G06T15/50 , G06T15/80
摘要： A fragment processor includes a fragment shader distributor, a fragment shader collector, and a plurality of fragment shader pipelines. Each fragment shader pipeline executes a fragment shader program on a segment of fragments. The plurality of fragment shader pipelines operate in parallel, executing the same or different fragment shader programs. The fragment shader distributor receives a stream of fragments from a rasterization unit and dispatches a portion of the stream of fragments to a selected fragment shader pipeline until the capacity of the selected fragment shader pipeline is reached. The fragment shader distributor then selects another fragment shader pipeline. The capacity of each of the fragment shader pipelines is limited by several different resources. As the fragment shader distributor dispatches fragments, it tracks the remaining available resources of the selected fragment shader pipeline. A fragment shader collector retrieves processed fragments from the plurality of fragment shader pipelines.
摘要翻译： 片段处理器包括片段着色器分配器，片段着色器收集器和多个片段着色器管线。 每个片段着色器流水线在片段片段上执行片段着色器程序。 多个片段着色器管线并行操作，执行相同或不同的片段着色器程序。 片段着色器分配器从光栅化单元接收片段流，并将片段流的一部分分派到所选择的片段着色器管线，直到达到所选片段着色器管线的容量。 片段着色器分配器然后选择另一个片段着色器管道。 每个片段着色器管道的容量受到几个不同的资源的限制。 当片段着色器分配器调度片段时，它会跟踪所选片段着色器管道的剩余可用资源。 片段着色器收集器从多个片段着色器管道中检索已处理的片段。
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公开(公告)号：US07576751B2
公开(公告)日：2009-08-18
申请号：US11532069
申请日：2006-09-14
CPC分类号： G06T3/40
摘要： A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within the fragment, affecting actual texture map coordinates or barycentric weights. Alternatively, a centroid sub-pixel sample position is determined based on coverage data for the pixel and a multisample mode. The centroid sub-pixel sample position is used to compute pixel or sub-pixel parameters for the fragment.
摘要翻译： 未被覆盖像素的一部分的原图覆盖的像素中心位置被移位以位于由图元和像素的交点形成的片段内。 调整像素中心的X，Y坐标以使像素中心位置位于片段内，影响实际纹理图坐标或重心权重。 或者，基于像素的覆盖数据和多采样模式来确定质心子像素采样位置。 质心子像素采样位置用于计算片段的像素或子像素参数。
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公开(公告)号：US07425966B2
公开(公告)日：2008-09-16
申请号：US10960857
申请日：2004-10-07
CPC分类号： G06T3/40
摘要： A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within the fragment, affecting actual texture map coordinates or barycentric weights. Alternatively, a centroid sub-pixel sample position is determined based on coverage data for the pixel and a multisample mode. The centroid sub-pixel sample position is used to compute pixel or sub-pixel parameters for the fragment.
摘要翻译： 未被覆盖像素的一部分的原图覆盖的像素中心位置被移位以位于由图元和像素的交点形成的片段内。 调整像素中心的X，Y坐标以使像素中心位置位于片段内，影响实际纹理图坐标或重心权重。 或者，基于像素的覆盖数据和多采样模式来确定质心子像素采样位置。 质心子像素采样位置用于计算片段的像素或子像素参数。
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公开(公告)号：US07624255B1
公开(公告)日：2009-11-24
申请号：US11076201
申请日：2005-03-09
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F8/445 , G06F9/3836 , G06F9/3867 , G06F9/3885 , G06T15/005
摘要： A system and method controls the scheduling of program instructions included in a shader program for execution by a processing pipeline. One or more fence instructions may be inserted into the shader program. Each fence instruction specifies a constraint that is applied to control the scheduling of another program instruction in the shader program. Controlling the scheduling of program instructions for execution by the processing pipeline may result in a more efficient use of computing resources and improved performance.
摘要翻译： 系统和方法控制包括在着色器程序中的程序指令的调度以供处理管线执行。 可以将一个或多个栅栏指令插入到着色器程序中。 每个栅栏指令都指定一个约束条件，用于控制着色器程序中另一个程序指令的调度。 控制由处理流水线执行的程序指令的调度可以导致计算资源的更有效的使用和改进的性能。
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公开(公告)号：US07646389B1
公开(公告)日：2010-01-12
申请号：US11133010
申请日：2005-05-18
CPC分类号： G09G5/363 , G06T15/04 , G06T2210/36 , G09G5/003 , G09G5/393
摘要： Methods and systems for texture mapping in a computer-implemented graphics pipeline are described. A sample group is identified as including a divergent pixel. A determination is made whether an operand of an instruction executing on the divergent pixel satisfies a condition. A scheme for determining a level of detail for the texture mapping is selected depending on whether or not the condition is satisfied.
摘要翻译： 描述了在计算机实现的图形管线中的纹理映射的方法和系统。 样本组被识别为包含发散像素。 确定在发散像素上执行的指令的操作数是否满足条件。 根据条件是否满足来选择用于确定纹理映射的细节级别的方案。
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9.发明授权Programmable shader having register forwarding for reduced register-file bandwidth consumption 有权可编程着色器具有寄存器转发功能，可减少寄存器文件带宽消耗公开(公告)号：US07623132B1
公开(公告)日：2009-11-24
申请号：US11019975
申请日：2004-12-20
CPC分类号： G09G5/363 , G06T15/005 , G06T15/80 , G09G5/39
摘要： A method and apparatus of operating a shader having multiple texture or shader processing stations. That method includes feeding the output of a texture or shader processing station directly into the input of another texture or shader processing station. Further, only a subset of the processing stations has access to a shader register file.
摘要翻译： 一种操作具有多个纹理或着色器处理站的着色器的方法和装置。 该方法包括将纹理或着色器处理站的输出直接馈送到另一个纹理或着色器处理站的输入。 此外，只有处理站的子集才能访问着色器寄存器文件。
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公开(公告)号：US07324113B1
公开(公告)日：2008-01-29
申请号：US11076200
申请日：2005-03-09
CPC分类号： G06T15/005 , G09G5/005 , G09G5/363 , G09G5/393
摘要： A method of optimizing perspective correction computations to be executed in a programmable fragment shader, identifying a sequence of program instructions; determining whether the sequence of program instructions can be optimized based on the status of the bit; sourcing one or more interpolated texture map coordinates to thereby disable the perspective correction computation comprising division by (1/w); and enabling the optimized execution of one of a plurality of perspective computation functions by a sought operation in a shader unit without division of the interpolated texture maps coordinates by (1/w). The optimized function includes able mapping, projective mapping, normalization, or scaling invariant operations.
摘要翻译： 一种优化在可编程片段着色器中执行的透视校正计算的方法，识别程序指令的序列; 确定是否可以基于位的状态来优化程序指令的序列; 提供一个或多个内插纹理贴图坐标，从而禁止包括除以（1 / w）的透视校正计算; 并且通过在着色器单元中的寻找操作来实现多个透视计算功能中的一个的优化执行，而不使内插纹理映射坐标乘以（1 / w）。 优化的功能包括能够映射，投影映射，归一化或缩放不变操作。
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