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公开(公告)号：US07385607B2
公开(公告)日：2008-06-10
申请号：US10938042
申请日：2004-09-10
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译： 公开了可扩展着色器架构。 根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。 着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。 着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。 着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。 着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。 每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。
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公开(公告)号：US07425966B2
公开(公告)日：2008-09-16
申请号：US10960857
申请日：2004-10-07
CPC分类号： G06T3/40
摘要： A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within the fragment, affecting actual texture map coordinates or barycentric weights. Alternatively, a centroid sub-pixel sample position is determined based on coverage data for the pixel and a multisample mode. The centroid sub-pixel sample position is used to compute pixel or sub-pixel parameters for the fragment.
摘要翻译： 未被覆盖像素的一部分的原图覆盖的像素中心位置被移位以位于由图元和像素的交点形成的片段内。 调整像素中心的X，Y坐标以使像素中心位置位于片段内，影响实际纹理图坐标或重心权重。 或者，基于像素的覆盖数据和多采样模式来确定质心子像素采样位置。 质心子像素采样位置用于计算片段的像素或子像素参数。
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公开(公告)号：US07576751B2
公开(公告)日：2009-08-18
申请号：US11532069
申请日：2006-09-14
CPC分类号： G06T3/40
摘要： A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within the fragment, affecting actual texture map coordinates or barycentric weights. Alternatively, a centroid sub-pixel sample position is determined based on coverage data for the pixel and a multisample mode. The centroid sub-pixel sample position is used to compute pixel or sub-pixel parameters for the fragment.
摘要翻译： 未被覆盖像素的一部分的原图覆盖的像素中心位置被移位以位于由图元和像素的交点形成的片段内。 调整像素中心的X，Y坐标以使像素中心位置位于片段内，影响实际纹理图坐标或重心权重。 或者，基于像素的覆盖数据和多采样模式来确定质心子像素采样位置。 质心子像素采样位置用于计算片段的像素或子像素参数。
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公开(公告)号：US07218291B2
公开(公告)日：2007-05-15
申请号：US10940070
申请日：2004-09-13
CPC分类号： G06T11/40 , G06T15/005 , G06T15/50 , G06T15/80
摘要： A fragment processor includes a fragment shader distributor, a fragment shader collector, and a plurality of fragment shader pipelines. Each fragment shader pipeline executes a fragment shader program on a segment of fragments. The plurality of fragment shader pipelines operate in parallel, executing the same or different fragment shader programs. The fragment shader distributor receives a stream of fragments from a rasterization unit and dispatches a portion of the stream of fragments to a selected fragment shader pipeline until the capacity of the selected fragment shader pipeline is reached. The fragment shader distributor then selects another fragment shader pipeline. The capacity of each of the fragment shader pipelines is limited by several different resources. As the fragment shader distributor dispatches fragments, it tracks the remaining available resources of the selected fragment shader pipeline. A fragment shader collector retrieves processed fragments from the plurality of fragment shader pipelines.
摘要翻译： 片段处理器包括片段着色器分配器，片段着色器收集器和多个片段着色器管线。 每个片段着色器流水线在片段片段上执行片段着色器程序。 多个片段着色器管线并行操作，执行相同或不同的片段着色器程序。 片段着色器分配器从光栅化单元接收片段流，并将片段流的一部分分派到所选择的片段着色器管线，直到达到所选片段着色器管线的容量。 片段着色器分配器然后选择另一个片段着色器管道。 每个片段着色器管道的容量受到几个不同的资源的限制。 当片段着色器分配器调度片段时，它会跟踪所选片段着色器管道的剩余可用资源。 片段着色器收集器从多个片段着色器管道中检索已处理的片段。
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公开(公告)号：US07852340B2
公开(公告)日：2010-12-14
申请号：US11957358
申请日：2007-12-14
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译： 公开了可扩展着色器架构。 根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。 着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。 着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。 着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。 着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。 每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。
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公开(公告)号：US07490208B1
公开(公告)日：2009-02-10
申请号：US10959560
申请日：2004-10-05
IPC分类号： G06F13/372 , G06F12/00
CPC分类号： G06F13/372
摘要： Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phases generated from a clock. In another embodiment, a semiconductor device includes the architecture for compact multi-ported register file. The semiconductor device comprises a plurality of register files. Each register file comprises a RAM comprising a port for read operations and for write operations. Moreover, each RAM serially performs N read operations and M write operations associated with one of a plurality of data groups using a corresponding clock phase of (N+M) clock phases generated from a clock. Further, the semiconductor device comprises an input staging unit for staging write data of one or more of the write operations. Continuing, the semiconductor device comprises an output staging unit for staging read data of one or more of the read operations. The semiconductor device can be a graphics processing unit (GPU).
摘要翻译： 公开了用于紧凑型多端口寄存器堆的架构。 在一个实施例中，寄存器文件包括单端口随机存取存储器（RAM）。 单端口RAM包括用于读取操作和写入操作的单个端口。 通过单个端口对给定的时钟执行单个读取或单个写入操作。 此外，单端口RAM使用从时钟产生的（N + M）个时钟相位的时钟相位来串行地执行与数据组相关联的N个读取操作和M个写入操作。 在另一个实施例中，半导体器件包括用于紧凑型多端口寄存器堆的结构。 半导体器件包括多个寄存器文件。 每个寄存器文件包括RAM，其包括用于读操作和写操作的端口。 此外，每个RAM使用从时钟生成的（N + M）个时钟相位的相应时钟相位，串行地执行与多个数据组之一相关联的N个读取操作和M个写入操作。 此外，半导体器件包括用于对一个或多个写入操作的写入数据进行分级的输入分段单元。 继续地，半导体器件包括用于对读取操作中的一个或多个读取数据进行分级的输出分段单元。 半导体器件可以是图形处理单元（GPU）。
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公开(公告)号：US08223150B2
公开(公告)日：2012-07-17
申请号：US13193524
申请日：2011-07-28
申请人： Brian Cabral , Amy J. Migdal , Rui M. Bastos , Karim M. Abdalla
发明人： Brian Cabral , Amy J. Migdal , Rui M. Bastos , Karim M. Abdalla
CPC分类号： G06T15/50 , G06F8/441 , G06T15/005 , G06T2210/32
摘要： An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.
摘要翻译： 一种用于将固定功能状态转换为着色器程序的装置和方法。 固定功能状态被接收和存储，当检测到新的着色器程序时，固定功能状态被转换为着色器程序指令。 由程序指令指定的寄存器被分配给着色器程序中的处理。 可以重新映射寄存器以更有效地使用寄存器存储空间。
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公开(公告)号：US08004523B1
公开(公告)日：2011-08-23
申请号：US11966905
申请日：2007-12-28
申请人： Brian Cabral , Amy J. Migdal , Rui M. Bastos , Karim M. Abdalla
发明人： Brian Cabral , Amy J. Migdal , Rui M. Bastos , Karim M. Abdalla
CPC分类号： G06T15/50 , G06F8/441 , G06T15/005 , G06T2210/32
摘要： An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.
摘要翻译： 一种用于将固定功能状态转换为着色器程序的装置和方法。 固定功能状态被接收和存储，当检测到新的着色器程序时，固定功能状态被转换成着色器程序指令。 由程序指令指定的寄存器被分配给着色器程序中的处理。 可以重新映射寄存器以更有效地使用寄存器存储空间。
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公开(公告)号：US07821520B1
公开(公告)日：2010-10-26
申请号：US11009471
申请日：2004-12-10
CPC分类号： G06T1/20
摘要： A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader processor and as a First-In First-Out (FIFO) buffer for a subsequent module. Some embodiments include automatic, programmable hardware conversion between numeric formats, for example, between floating point data and fixed point data.
摘要翻译： 一种新的，有用的和不可见的着色器处理器架构，其具有着色器寄存器文件，其既用作内部存储寄存器文件，用于在着色器处理器内临时存储数据，并作为先进先出（FIFO）缓冲器，用于后续 模块。 一些实施例包括数字格式之间的自动，可编程硬件转换，例如在浮点数据和固定点数据之间。
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公开(公告)号：US07542042B1
公开(公告)日：2009-06-02
申请号：US10985575
申请日：2004-11-10
CPC分类号： G06T1/20 , G06F9/5044 , G06T15/005 , G09G5/14 , G09G2360/121 , G09G2360/18
摘要： A new method of operating a fragment shader to produce complex video content comprised of a video image or images, such as from a DVD player, that overlays a fragment shader-processed background. Pixels are fragment shader-processed during one loop or set of loops through a texture processing stations to produce a fragment shader-processed background. Then, at least some of those pixels are merged with the video or images to produce complex video content. The resulting complex image is then made available for further processing.
摘要翻译： 操作片段着色器以产生由视频图像或诸如DVD播放器的图像组成的复杂视频内容的新方法，其叠加片段着色器处理的背景。 像素是通过纹理处理站的一个循环或一组循环中的片段着色器处理，以产生片段着色器处理的背景。 然后，这些像素中的至少一些与视频或图像合并以产生复杂的视频内容。 然后使得到的复杂图像可用于进一步处理。
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