公开(公告)号：US6081562A

公开(公告)日：2000-06-27

申请号：US956309

申请日：1997-10-22

申请人： Runsheng He ,  Joao R. Cruz

发明人： Runsheng He ,  Joao R. Cruz

IPC分类号： H03M13/23 ,  H03M13/41 ,  H04L25/03 ,  H03D1/00 ,  H04L27/06

CPC分类号： H03M13/6343 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6502 ,  H04L25/03229

摘要： A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

公开(公告)号：US06711213B2

公开(公告)日：2004-03-23

申请号：US10347889

申请日：2003-01-21

申请人： Runsheng He ,  Joao R. Cruz

发明人： Runsheng He ,  Joao R. Cruz

IPC分类号： H04L512

CPC分类号： H03M13/6343 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6502 ,  H04L25/03229

摘要： A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

摘要翻译： 提供了一种用于符号间干扰信道的简化状态维特比检测器的设计方法和实现系统。 该方法使用补码状态分组技术，其包括找到补码状态之间的状态距离的步骤; 通过将状态距离不小于最小自由距离分组补码状态来形成缩小状态网格; 并保持状态距离小于最小自由距离不变的补码状态。 所得到的降维态维特比检测器与全状态维特比检测器相比具有可忽略的性能损失，而复杂度降低了约两倍。

公开(公告)号：US06597742B1

公开(公告)日：2003-07-22

申请号：US09603703

申请日：2000-06-27

申请人： Runsheng He ,  Joao R. Cruz

发明人： Runsheng He ,  Joao R. Cruz

IPC分类号： H04L512

CPC分类号： H03M13/6343 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6502 ,  H04L25/03229

摘要： A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

摘要翻译： 提供了一种用于符号间干扰信道的简化状态维特比检测器的设计方法和实现系统。 该方法使用补码状态分组技术，其包括找到补码状态之间的状态距离的步骤; 通过将状态距离不小于最小自由距离分组补码状态来形成缩小状态网格; 并保持状态距离小于最小自由距离不变的补码状态。 所得到的降维态维特比检测器与全状态维特比检测器相比具有可忽略的性能损失，而复杂度降低了约两倍。

公开(公告)号：US5982818A

公开(公告)日：1999-11-09

申请号：US779510

申请日：1997-01-07

申请人： Daniel J. Krueger ,  Joao R. Cruz

发明人： Daniel J. Krueger ,  Joao R. Cruz

IPC分类号： H04L27/00 ,  H03M13/23 ,  H04B3/04 ,  H04B7/005 ,  H04L5/12 ,  H04L25/497 ,  H04L27/36

CPC分类号： H03M13/256 ,  H04L27/3416

摘要： A method of design and implementation of trellis codes for intersymbol interference channels is provided wherein a set of input vectors is mapped to a set of output vectors comprising the steps of forming a minimized basis having a set of minimized basis vectors configured for a set of channel output signals corresponding to the set of output vectors; selecting the smallest member of the set of minimized basis vectors as a coset vector; forming a partition basis by adding the coset vector to at least one member of the set of the minimized basis vectors; and forming a subsequent minimized basis from the partition basis. These codes circumvent the necessity for intersymbol interference removal, thereby reducing equalization complexity.

摘要翻译： 提供了一种用于符号间干扰信道的网格码的设计和实现的方法，其中一组输入向量被映射到一组输出向量，包括以下步骤：形成具有被配置用于一组信道的最小化基向量的最小化基 对应于该组输出向量的输出信号; 选择最小化基向量集合中的最小成员作为陪集向量; 通过将所述陪集向量加到所述最小化基向量集合中的至少一个成员来形成分区基; 以及从分区基础形成随后的最小化基础。 这些代码规避了符号间干扰去除的必要性，从而降低均衡复杂度。

公开(公告)号：US5621580A

公开(公告)日：1997-04-15

申请号：US296512

申请日：1994-08-26

申请人： Joao R. Cruz ,  Daniel J. Krueger

发明人： Joao R. Cruz ,  Daniel J. Krueger

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14

CPC分类号： G11B20/1492 ,  G11B20/10009 ,  G11B5/09

摘要： A digital magnetic recording system comprises an input for a binary-encoded data signal comprising two symbols. The binary signal is converted, using a binary-to-ternary convolutional encoder, to a ternary signal comprising three symbols. The ternary signal is recorded onto a magnetic medium wherein two symbols are recorded using conventional saturation recording and a third symbol is recorded using a nonoriented state. The nonoriented state results from the application to the medium of a high-frequency oscillating magnetic flux. The recorded signal is subsequently reproduced and equalized. A Viterbi algorithm is used to convert the equalized signal back to the original binary signal which is then output from the system.

摘要翻译： 数字磁记录系统包括用于二进制编码数据信号的输入，包括两个符号。 使用二进制到三进制卷积编码器将二进制信号转换成包括三个符号的三进制信号。 将三元信号记录在磁性介质上，其中使用常规饱和记录记录两个符号，并且使用非取向状态记录第三符号。 非取向状态是由应用于高频振荡磁通的介质而产生的。 记录的信号随后被再现和均衡。 维特比算法用于将均衡的信号转换回原来的二进制信号，然后从系统输出。