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公开(公告)号：US5075846A
公开(公告)日：1991-12-24
申请号：US414335
申请日：1989-09-29
申请人： Russell A. Reininger , William B. Ledbetter, Jr. , Robin W. Edenfield , Van B. Shahan , Ralph C. McGarity , Eric E. Quintana
发明人： Russell A. Reininger , William B. Ledbetter, Jr. , Robin W. Edenfield , Van B. Shahan , Ralph C. McGarity , Eric E. Quintana
CPC分类号： G06F9/3802 , G06F12/0877 , G06F9/3834
摘要： A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.
摘要翻译： 提供了具有基于页面的序列化属性的数据处理器。 一组页面描述符和透明的翻译寄存器将序列化属性编码为高速缓存模式。 数据处理器是一个流水线机器，具有至少两个功能单元，它们彼此独立地工作。 功能单元向访问控制器发出访问存储在外部存储器中的信息的请求。 访问控制器用作仲裁机制，并且根据功能单元的请求的发布顺序来授予功能单元的请求。 当存储器访问在页面描述符中被标记为序列化时，访问控制器推迟序列化访问，直到指令序列中所有待处理的存储器访问完成为止。 所有待处理的请求随后以预定的顺序完成，而与功能单元的请求的发布顺序无关，并且完成所有适当的异常处理。 然后完成推迟的序列化访问。
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2.发明授权Parallel method and apparatus for detecting and completing floating point operations involving special operands 失效用于检测和完成涉及特殊操作数的浮点运算的并行方法和装置
公开(公告)号：US5339266A
公开(公告)日：1994-08-16
申请号：US158324
申请日：1993-11-29
CPC分类号： G06F7/483 , G06F7/49905
摘要： A method and apparatus for detecting and completing floating point operations involving special floating point operands is performed in parallel, via a circuit (24), to the operation of at least one floating point mathematical unit (18, 20or 22). The floating point control (30) along with registers (14 and 16) provide floating point operands and floating point control to the mathematical units (18, 20, and 22). If the mathematical units (18, 20, and 22) cannot perform a proper floating point calculation because of the presence of a special operand, then the circuit (24) will detect the special operand and complete the floating point operation in a proper manner by communicating with the floating point control unit (30).
摘要翻译： 用于检测和完成涉及特殊浮点操作数的浮点运算的方法和装置通过电路（24）并行地执行至少一个浮点数学单元（18,20或22）的操作。 浮点控制（30）以及寄存器（14和16）为数学单元（18,20和22）提供浮点运算和浮点控制。 如果数学单元（18,20和22）由于存在特殊操作数而不能执行适当的浮点计算，则电路（24）将检测特殊操作数，并以适当方式完成浮点运算 与浮点控制单元（30）通信。
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公开(公告)号：US5539684A
公开(公告)日：1996-07-23
申请号：US529469
申请日：1995-09-18
CPC分类号： G06F7/535 , G06F5/012 , G06F7/5525 , G06F7/4873
摘要： A data processing system (10) has a circuit for determining floating point exponents for divide operations and square root operations. The circuit has two input multiplexers (26 and 28) which provide exponent information or constants to an adder (30). The exponent information and constants are processed by the adder (30) to output three possible exponent values for either a divide operation or a square root operation. The three possible exponent values are stored in three registers (34, 36, and 38). A multiplexer (40) used mantissa rounding and normalizing information to determine which exponent of the three possible exponent values are correct for the current floating point calculation.
摘要翻译： 数据处理系统（10）具有用于确定用于除法运算和平方根操作的浮点指数的电路。 该电路具有向加法器（30）提供指数信息或常数的两个输入多路复用器（26和28）。 加法器（30）处理指数信息和常数，以输出除法运算或平方根运算的三个可能的指数值。 三个可能的指数值存储在三个寄存器（34,36和38）中。 多路复用器（40）使用尾数舍入和归一化信息来确定三个可能指数值的指数对于当前浮点计算是否正确。
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