公开(公告)号：US5075846A

公开(公告)日：1991-12-24

申请号：US414335

申请日：1989-09-29

申请人： Russell A. Reininger ,  William B. Ledbetter, Jr. ,  Robin W. Edenfield ,  Van B. Shahan ,  Ralph C. McGarity ,  Eric E. Quintana

发明人： Russell A. Reininger ,  William B. Ledbetter, Jr. ,  Robin W. Edenfield ,  Van B. Shahan ,  Ralph C. McGarity ,  Eric E. Quintana

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3802 ,  G06F12/0877 ,  G06F9/3834

摘要： A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.

摘要翻译： 提供了具有基于页面的序列化属性的数据处理器。 一组页面描述符和透明的翻译寄存器将序列化属性编码为高速缓存模式。 数据处理器是一个流水线机器，具有至少两个功能单元，它们彼此独立地工作。 功能单元向访问控制器发出访问存储在外部存储器中的信息的请求。 访问控制器用作仲裁机制，并且根据功能单元的请求的发布顺序来授予功能单元的请求。 当存储器访问在页面描述符中被标记为序列化时，访问控制器推迟序列化访问，直到指令序列中所有待处理的存储器访问完成为止。 所有待处理的请求随后以预定的顺序完成，而与功能单元的请求的发布顺序无关，并且完成所有适当的异常处理。 然后完成推迟的序列化访问。

公开(公告)号：US5086407A

公开(公告)日：1992-02-04

申请号：US361539

申请日：1989-06-05

申请人： Ralph C. McGarity ,  William B. Ledbetter, Jr. ,  Steven C. McMahan ,  Michael G. Gallup ,  Russell Stanphill ,  James G. Gay

发明人： Ralph C. McGarity ,  William B. Ledbetter, Jr. ,  Steven C. McMahan ,  Michael G. Gallup ,  Russell Stanphill ,  James G. Gay

IPC分类号： G06F13/36 ,  G06F13/42 ,  G06F15/78

CPC分类号： G06F13/4208 ,  G06F15/7832

摘要： A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.

摘要翻译： 具有可被编程为将电路的地址和数据总线端子置于两种模式之一的输入的单芯片数据处理器集成电路。 在第一或多路复用模式下，电路的地址和数据终端直接连接，并且当两者都写入外部电路时，地址位与数据位进行时分复用。 在第二或正常模式下，电路的地址和数据端子不连接，地址位与电路无关地与电路通信的数据位通信。 需要集成电路外部的电路来实现复用模式。 控制部分确保当电路处于复用模式时避免位冲突。

公开(公告)号：US5606682A

公开(公告)日：1997-02-25

申请号：US418049

申请日：1995-04-07

申请人： Ralph C. McGarity

发明人： Ralph C. McGarity

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3806 ,  G06F12/0875 ,  G06F9/30054

摘要： A data processor (10) has a branch and link address cache ("BLAC") (40) and a BTAC (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine return instructions each time data processor executes a particular subroutine. Upon the second call of the subroutine, control logic (44) stores the half of the data pair identifying the subroutine return instruction and data identifying the return address in the BTAC. The data processor is thereby able to predict the target address of a subroutine return instruction as it is able to predict the target address of traditional branch instructions.

摘要翻译： 数据处理器（10）具有分支和链接地址高速缓存（“BLAC”）（40）和用于存储最近遇到的数量的提取地址目标地址对的BTAC（48）。 每当数据处理器执行特定子程序时，BLAC缓冲数据对，识别相应的子程序调用和子程序返回指令。 在子程序的第二次调用时，控制逻辑（44）将识别子程序返回指令的数据对的一半和识别返回地址的数据存储在BTAC中。 因此，数据处理器能够预测子程序返回指令的目标地址，因为它能够预测传统分支指令的目标地址。

公开(公告)号：US5687349A

公开(公告)日：1997-11-11

申请号：US718756

申请日：1996-09-23

申请人： Ralph C. McGarity

发明人： Ralph C. McGarity

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3806 ,  G06F12/0875 ,  G06F9/30054

摘要： A data processor (10) has a branch and link address cache (.sup.++ BLAC.sup.++) (40) and a Branch Target Address Cache (BTAC) (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine return instructions each time data processor executes a particular subroutine. Upon the second call of the subroutine, control logic (44) stores the half of the data pair identifying the subroutine return instruction and data identifying the return address in the BTAC. The data processor is thereby able to predict the target address of a subroutine return instruction as it is able to predict the target address of traditional branch instructions.

摘要翻译： 数据处理器（10）具有分支和链接地址缓存（++ BLAC ++）（40）和分支目标地址缓存（BTAC）（48），用于存储最近遇到的多个获取地址目标地址对。 每当数据处理器执行特定子程序时，BLAC缓冲数据对，识别相应的子程序调用和子程序返回指令。 在子程序的第二次调用时，控制逻辑（44）将识别子程序返回指令的数据对的一半和识别返回地址的数据存储在BTAC中。 因此，数据处理器能够预测子程序返回指令的目标地址，因为它能够预测传统分支指令的目标地址。