-
公开(公告)号：US4594660A
公开(公告)日：1986-06-10
申请号：US434129
申请日：1982-10-13
CPC分类号： G06F9/3885 , G06F9/3863
摘要： A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute instructions issued to them in order of issuance by the pipeline and in parallel. As instructions are issued to the execution units, the operation code identifying each instruction is also issued in program order to an instruction execution queue of the collector. The results of the execution of each instruction by an execution unit are stored in a result stack associated with each execution unit. Collector control causes the results of the execution of instructions to program visible registers to be stored in a master safe store register in program order which is determined by the order of instructions stored in the instruction execution stack on a first-in, first-out basis. The collector also issues write commands to write results of the execution of instructions into memory in program order.
摘要翻译： 用于数字数据处理系统的流水线中央处理单元的结果的收集器。 处理器具有多个执行单元，每个执行单元执行处理器的指令集的不同指令集。 执行单元按照管道发布的顺序执行发给他们的指令并行执行。 当向执行单元发出指令时，识别每条指令的操作代码也以程序顺序发布到收集器的指令执行队列。 由执行单元执行每条指令的结果存储在与每个执行单元相关联的结果堆栈中。 收集器控制导致执行指令的结果将可见寄存器编程存储在主安全存储寄存器中，程序顺序由存储在指令执行堆栈中的指令顺序以先进先出为基础确定 。 收集器还发出写入命令，以按程序顺序将指令的执行结果写入存储器。
-
2.发明授权Method and apparatus for initiating the execution of instructions using a central pipeline execution unit 失效用于使用中央流水线执行单元发起指令执行的方法和装置
公开(公告)号：US4471432A
公开(公告)日：1984-09-11
申请号：US434196
申请日：1982-10-13
申请人： John E. Wilhite , William A. Shelly , Russell W. Guenthner , Leonard G. Trubisky , Joseph C. Circello
发明人： John E. Wilhite , William A. Shelly , Russell W. Guenthner , Leonard G. Trubisky , Joseph C. Circello
CPC分类号： G06F9/3867
摘要： A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction field are obtained in program order from an instruction fetch unit of the CPU. In a first stage, requiring one clock period, the address information of an instruction is utilized to form the carrys and sums of an effective address and to initiate the formation of a virtual address. Concurrently, the instruction field is decoded to produce memory command signals and data alignment signals. In a second stage, the formation of the effective and virtual addresses initiated in the first stage is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU. Also during the second stage, memory command signals are sent to the cache unit and the instruction field is converted to an execution code for one of a plurality of execution units, and the execution unit to execute the code is designated. In a third stage, the virtual address is converted to a physical address, or real page number, which is transmitted to the cache unit. The execution code is sent to the designated execution unit; however, if the execution unit is the central unit, the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. In the fourth stage, data alignment control signals are sent to a distributor of the central execution pipeline unit.
摘要翻译： 一种用于启动通用数字数据处理系统的同步中央处理器单元（CPU）的指令执行的方法和中央执行流水线单元。 从CPU的指令提取单元以程序顺序获取包含地址信息和指令字段的指令。 在需要一个时钟周期的第一阶段中，使用指令的地址信息来形成有效地址的进位和和并且启动虚拟地址的形成。 同时，指令字段被解码以产生存储器命令信号和数据对准信号。 在第二阶段中，完成在第一阶段中发起的有效和虚拟地址的形成，虚拟地址的字地址部分被发送到CPU的高速缓存单元。 此外，在第二阶段期间，存储器命令信号被发送到高速缓存单元，并且指令字段被转换为多个执行单元之一的执行代码，并且指定执行代码执行代码。 在第三阶段中，将虚拟地址转换为物理地址或实际页号，该地址被发送到高速缓存单元。 执行代码被发送到指定的执行单元; 然而，如果执行单元是中央单元，则执行单元是中央单元，该单元的执行代码被转换为执行单元控制信号。 在第四阶段，将数据对准控制信号发送到中央执行流水线单元的分配器。
-
公开(公告)号：US4527238A
公开(公告)日：1985-07-02
申请号：US470353
申请日：1983-02-28
CPC分类号： G06F12/0848
摘要： Cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the cache are equal in capacity. The two parts of the cache, designated I-Cache and O-Cache, are semi-independent in their operation and include arrangements for effecting synchronized searches, they can accommodate up to three separate operations substantially simultaneously. Each cache unit has a directory and a data array with the directory and data array being separately addressable. Each cache unit may be subjected to a primary and to one or more secondary concurrent uses with the secondary uses prioritized. Data is stored in the cache unit on a so-called store-into basis wherein data obtained from the main memory is operated upon and stored in the cache without returning the operated upon data to the main memory unit until subsequent transactions require such return.
摘要翻译： 高速缓存存储器包括双或两部分缓存，其中一部分高速缓存主要被指定用于指令数据，而另一部分主要被指定用于操作数数据，而不是排他地。 为了最大的运行速度，缓存的两部分容量相等。 高速缓存的两部分，指定为I-Cache和O-Cache，它们的操作是半独立的，包括实现同步搜索的安排，它们可以同时容纳多达三个独立的操作。 每个高速缓存单元都有一个目录和一个数据阵列，目录和数据阵列是可单独寻址的。 每个高速缓存单元可以经受主要和一个或多个辅助并发使用，次要使用被优先化。 数据以所谓的存储方式存储在高速缓存单元中，其中从主存储器获得的数据被操作并存储在高速缓存中，而不将操作的数据返回到主存储器单元，直到后续的事务需要这样的返回。
-
公开(公告)号：US4298952A
公开(公告)日：1981-11-03
申请号：US102300
申请日：1979-12-10
CPC分类号： G06F7/505 , G06F2207/3836
摘要： A one's complement adder for adding two binary numbers A.sub.i, B.sub.i in the one's complement system is constructed from a conventional adder circuit by connecting the generate output signal G produced by the adder to the carry-in terminal of the adder. The value of the generate signal is independent of the signal applied to the carry-in terminal which prevents the adder from exhibiting sequential or indeterminate behavior.
摘要翻译： 通过将由加法器产生的生成输出信号G连接到加法器的进位端，通过常规加法器电路构成用于在补码系统中加上两个二进制数Ai，Bi的补码加法器。 生成信号的值与施加到输入端子的信号无关，防止加法器显示顺序或不确定的行为。
-
5.发明授权
公开(公告)号：US4538238A
公开(公告)日：1985-08-27
申请号：US458794
申请日：1983-01-18
CPC分类号： G06F7/727
摘要： Method and apparatus for calculating the residue of a signed binary number of "n" bits with respect to a given check base m where m=2.sup.b -1. The bits of the binary number excluding the sign bit are partitioned into number segments, each of b bits starting with the least significant bit. If (n-1) is not an even multiple of b, higher order bit positions of the number segment containing the next most significant bit of the binary number are filled with logical zeros. A sign segment of b bits is formed. Both number and sign segments have boundaries. The bit position in the sign segment relative to a sign segment boundary which corresponds to the bit position of the sign bit "s" relative to the nearest boundary of a number segment is filled with a logical zero. All other bit positions of the sign segment are filled with the sign bit. The number and sign segments are applied to carry save adders to reduce the number segments and sign segment to a single sum segment and a single rotated carry segment. A rotated carry segment is a carry segment produced by a carry save adder, the most significant bit of which becomes the least significant bit of the rotated carry segment. The other bits of the carry segment and their significance are increased by one in the rotated carry segment. Carry segments produced by carry save adders of one level are converted to rotated carry segments before being applied to a carry save or full adder of a lower level. The single sum segment and single rotated carry segment produced by the lowest level carry save adder is applied to a one's complement adder. The b bit output of the one's complement adder is the residue of the signed binary number to the check base (2.sup.b -1).
摘要翻译： 用于计算相对于m = 2b-1的给定检验基数m的带符号二进制数“n”位的残差的方法和装置。 除符号位之外的二进制数的位被分割为数字段，每个b位以最低有效位开始。 如果（n-1）不是b的偶数倍，则包含二进制数的下一个最高有效位的数字段的高位位置被填充有逻辑0。 形成b位的符号段。 数字和符号段都有边界。 符号段相对于符号段边界相对于符号位“s”相对于数字段的最近边界的位位置的位位置用逻辑0填充。 符号段的所有其他位位置都用符号位填充。 数字和符号段被应用于携带保存加法器以减少数字段并将段标记到单个和段和单个旋转进位段。 旋转的进位段是由进位保存加法器产生的进位段，其最高有效位变为旋转进位段的最低有效位。 进位段的其他位及其重要性在旋转进位段增加1。 由一个级别的进位保存加法器产生的进位段在应用于较低级别的进位保存或全加器之前被转换为旋转的进位段。 由最低电平进位保存加法器产生的单个和段和单个旋转进位段应用于一个补码加法器。 补码加法器的b位输出是到校验基（2b-1）的带符号二进制数的残差。
-
6.发明授权Method and apparatus enabling multi threaded program execution for a Cobol program including OpenMP directives by utilizing a two-stage compilation process 有权通过利用两阶段编译过程，可以实现包括OpenMP指令在内的Cobol程序的多线程程序执行的方法和装置公开(公告)号：US08869126B2
公开(公告)日：2014-10-21
申请号：US13729490
申请日：2012-12-28
申请人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
发明人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.
摘要翻译： 公开了一种用于编译原始Cobol程序的方法和装置，其支持通过使用多个处理线程在执行期间通过增加的并行性来提高性能。 该方法包括两阶段编译过程，第一个专业编译器/翻译器的第一个编译/翻译步骤，将包含并行化指令的Cobol源程序作为输入，并以第二计算机编程语言生成中间计算机程序作为输出， 中间程序包括第二计算机编程语言中的并行化指令。 然后使用提供对第二编程语言中描述的并行性的支持的所选择的第二编译器来编译中间程序。 该方法可以允许在原始Cobol程序或中间程序中使用用作并行指令的编译指示给编译器。
-
7.发明授权Method and apparatus providing COBOL decimal type arithmetic functions with improved performance 有权提供具有改进性能的COBOL十进制算术函数的方法和装置公开(公告)号：US08856759B2
公开(公告)日：2014-10-07
申请号：US12658017
申请日：2010-02-01
CPC分类号： G06F8/49 , G06F8/41 , G06F8/4441 , G06F9/4484
摘要： A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.
摘要翻译： 公开了一种方法和装置，其通过计算机系统提供包括十进制数字变量的计算的算术计算性能的改进。 至少一个实施例的改进包括与特殊的十进制数字子程序库协同使用特殊的编译器。 编译器基于比较多个十进制变量的比对来提供比较对齐信息。 然后，十进制子程序库可以通过利用编译器在编译器时比较的信息在运行时提供改进的性能，而不是在运行时重复进行这些计算。
-
8.发明申请Method and apparatus providing COBOL decimal type arithmetic functions with improved performance 有权提供具有改进性能的COBOL十进制算术函数的方法和装置公开(公告)号：US20110191755A1
公开(公告)日：2011-08-04
申请号：US12658017
申请日：2010-02-01
IPC分类号： G06F9/45
CPC分类号： G06F8/49 , G06F8/41 , G06F8/4441 , G06F9/4484
摘要： A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.
摘要翻译： 公开了一种方法和装置，其通过计算机系统提供包括十进制数字变量的计算的算术计算性能的改进。 至少一个实施例的改进包括与特殊的十进制数字子程序库协同使用特殊的编译器。 编译器基于比较多个十进制变量的比对来提供比较对齐信息。 然后，十进制子程序库可以通过利用编译器在编译器时比较的信息在运行时提供改进的性能，而不是在运行时重复进行这些计算。
-
9.发明授权Central processing unit using dual basic processing units and combined result bus 失效中央处理单元采用双基本处理单元和组合结果总线
公开(公告)号：US5435000A
公开(公告)日：1995-07-18
申请号：US65105
申请日：1993-05-19
CPC分类号： G06F11/1633 , G06F12/0848 , H04L1/22
摘要： In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs.
摘要翻译： 为了在包含重复的BPU的CPU中验证完整性的数据操作结果，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作操作，则采用两个高速缓存单元。 每个缓存单元专用于处理半字节的信息，并且包含高度可靠的数据验证逻辑，而不需要从每个BPU提供双字宽输出总线。 通过将每个缓存单元专用于处理半字节的信息来获得降低每个VLSI芯片的引导计数的这个特征。 每个缓存单元包括逐位比较电路，用于在单精度操作的情况下验证从两个BPU接收的半字节结果，并且在双精度操作的情况下，一个高速缓存单元采用相同的逐位比较， 位比较电路，用于两个缓存单元，验证从两个BPU接收到的结果奇偶校验位，并因此验证半字节结果。
-
10.发明授权Method for translating a cobol source program into readable and maintainable program code in an object oriented second programming language 有权将cobol源程序转换为面向对象的第二编程语言中的可读和可维护程序代码的方法公开(公告)号：US09182962B2
公开(公告)日：2015-11-10
申请号：US13314041
申请日：2011-12-07
申请人： Todd Bradley Kneisel , Cynthia S. Guenthner , Albert Henry John Wigchert , Nicholas John Colasacco , Russell W. Guenthner , John Edward Heath , Clinton B. Eckard
发明人： Todd Bradley Kneisel , Cynthia S. Guenthner , Albert Henry John Wigchert , Nicholas John Colasacco , Russell W. Guenthner , John Edward Heath , Clinton B. Eckard
摘要： A method is disclosed for translating by a computer system of a COBOL computer program into a translated computer program in a readable and maintainable syntax in an object oriented programming language. The translated program including variable names equivalent to the original COBOL variable names and with attributes described in COBOL syntax. The translating method further providing for memory allocation in the translated computer program for storage of “COBOL” variables compatible with that of the original COBOL program; a description of program flow that is readable, and utilizing arithmetic operators to describe operations between COBOL variables. Also disclosed is a special object oriented run-time library for creating and performing operations between COBOL numeric objects, including maintaining storage of variable content in the original COBOL format, and for enabling readability of the translated source code by allowing arguments for variable type descriptions to be expressed in COBOL syntax.
摘要翻译： 公开了一种通过计算机系统将COBOL计算机程序翻译成面向对象编程语言的可读和可维护语法的翻译计算机程序的方法。 翻译的程序包括与原始COBOL变量名称等效的变量名称，并具有COBOL语法中描述的属性。 翻译方法进一步提供翻译的计算机程序中的存储器分配，用于存储与原始COBOL程序兼容的“COBOL”变量; 描述可读的程序流程，并利用算术运算符来描述COBOL变量之间的操作。 还公开了一种特殊的面向对象的运行时库，用于在COBOL数字对象之间创建和执行操作，包括保持原始COBOL格式的可变内容的存储，以及通过允许变量类型描述的参数来实现所翻译的源代码的可读性 用COBOL语法表达。
-
-
-
-
-
-
-
-
-
搜索结果
44 条记录 (耗时 0.028 秒)
