Method and apparatus for predication using micro-operations
    2.
    发明申请
    Method and apparatus for predication using micro-operations 有权
    使用微操作进行预测的方法和装置

    公开(公告)号:US20050081017A1

    公开(公告)日:2005-04-14

    申请号:US10685654

    申请日:2003-10-14

    IPC分类号: G06F9/30 G06F9/312 G06F9/38

    摘要: Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

    摘要翻译: 公开了一种用于使用微操作来实现预定指令的装置,系统和方法。 微码引擎接收指令,分解指令,并产生多个微操作来实现该指令。 每个分解的微操作指示单个目的地寄存器。 对于预测指令,分解的微操作包括在两个潜在输出值之间选择的“条件移动”微操作。 除了在一个潜在输出值是常数的情况下,用于预测指令的分解的微操作还包括将目的地寄存器的输入值保存在临时变量中的附加指令。 对于至少一个实施例,用于预测指令的限定谓词附加到存储在临时寄存器中的输入值。

    Renaming for register with multiple bit fields
    6.
    发明申请
    Renaming for register with multiple bit fields 有权
    重命名为多个位字段注册

    公开(公告)号:US20050027968A1

    公开(公告)日:2005-02-03

    申请号:US10632432

    申请日:2003-07-31

    IPC分类号: G06F9/30 G06F9/32 G06F9/38

    摘要: An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both partial-bit accesses and bulk-bit accesses to bits of the register. Rename logic utilizes a rename map table associated with the logical register to be renamed and also includes a plurality of physical rename registers. They physical rename registers include a set of skinny physical rename registers to be used for renaming for partial-bit writes. The physical rename registers also include a set of fat physical rename registers to be used for renaming for bulk-bit writes. Additional sizes of physical rename registers may also be employed. The entries of the single physical rename map table may point to either fat or skinny physical rename registers.

    摘要翻译: 提供了一种装置和方法,用于重命名允许不同长度的比特访问的逻辑寄存器,例如谓词寄存器。 重命名逻辑支持对部分位访问和对寄存器的位的批量访问进行重命名。 重命名逻辑利用与逻辑寄存器相关联的重命名映射表来重命名,并且还包括多个物理重命名寄存器。 它们的物理重命名寄存器包括一组用于部分位写入重命名的瘦物理重命名寄存器。 物理重命名寄存器还包括一组用于批量位写入重命名的胖物理重命名寄存器。 还可以使用附加大小的物理重命名寄存器。 单个物理重命名映射表的条目可能指向胖或瘦身体重命名寄存器。