公开(公告)号：US20100164010A1

公开(公告)日：2010-07-01

申请号：US12704677

申请日：2010-02-12

申请人： Ryota Watanabe ,  Taiki Komoda ,  Amane Oishi ,  Yasunori Okayama

发明人： Ryota Watanabe ,  Taiki Komoda ,  Amane Oishi ,  Yasunori Okayama

IPC分类号： H01L27/092

CPC分类号： H01L29/7833 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

摘要： A semiconductor device includes a substrate, a gate electrode formed on the substrate, a source region and a drain region formed in the substrate, the source region and the drain region formed located on the both side of the gate electrode, a first insulating film formed on the substrate, the first insulating film for generating a stress in a channel region under the gate electrode, a contact formed on the source region and the drain region, and the contact formed so that an amount of the first insulating film formed on the source region is larger than an amount of the first insulating film formed on the drain region.

摘要翻译： 半导体器件包括衬底，形成在衬底上的栅电极，形成在衬底中的源极区和漏极区，形成在栅电极的两侧上的源区和漏区，形成的第一绝缘膜 在基板上形成用于在栅电极下方的沟道区域产生应力的第一绝缘膜，形成在源极区域和漏极区域上的接触，以及形成为使得形成在源极上的第一绝缘膜的量 区域大于形成在漏极区域上的第一绝缘膜的量。

公开(公告)号：US20070102726A1

公开(公告)日：2007-05-10

申请号：US11590060

申请日：2006-10-31

申请人： Ryota Watanabe ,  Taiki Komoda ,  Amane Oishi ,  Yasunori Okayama

发明人： Ryota Watanabe ,  Taiki Komoda ,  Amane Oishi ,  Yasunori Okayama

IPC分类号： H01L29/739

CPC分类号： H01L29/7833 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

摘要： A semiconductor device includes a substrate, a gate electrode formed on the substrate, a source region and a drain region formed in the substrate, the source region and the drain region formed located on the both side of the gate electrode, a first insulating film formed on the substrate, the first insulating film for generating a stress in a channel region under the gate electrode, a contact formed on the source region and the drain region, and the contact formed so that an amount of the first insulating film formed on the source region is larger than an amount of the first insulating film formed on the drain region.

摘要翻译： 半导体器件包括衬底，形成在衬底上的栅电极，形成在衬底中的源极区和漏极区，形成在栅电极的两侧上的源区和漏区，形成的第一绝缘膜 在基板上形成用于在栅电极下方的沟道区域产生应力的第一绝缘膜，形成在源极区域和漏极区域上的接触，以及形成为使得形成在源极上的第一绝缘膜的量 区域大于形成在漏极区域上的第一绝缘膜的量。

公开(公告)号：US20060194398A1

公开(公告)日：2006-08-31

申请号：US11264377

申请日：2005-11-02

申请人： Amane Oishi ,  Taiki Komoda

发明人： Amane Oishi ,  Taiki Komoda

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/266 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66598

摘要： A semiconductor device which has a source/drain extension structure suitable for miniaturization, is provided a semiconductor device comprising a gate electrode formed on a semiconductor substrate of a first conductivity type via a gate insulator, a semiconductor region of a second conductivity type comprising first and second semiconductor areas, wherein the first semiconductor area is formed in the semiconductor substrate outside the gate electrode and whose junction depth becomes deeper as apart from the gate electrode, and wherein the second semiconductor area is disposed outside the first semiconductor area and whose junction depth is substantially constant, and an insulator formed to cover a part of the first semiconductor area and in contact with a side face of the gate electrode.

摘要翻译： 具有适于小型化的源极/漏极延伸结构的半导体器件提供有半导体器件，其包括通过栅极绝缘体形成在第一导电类型的半导体衬底上的栅电极，第二导电类型的半导体区域，包括第一和 第二半导体区域，其中所述第一半导体区域形成在所述半导体衬底的栅电极外部并且其结深度与所述栅电极分开更深，并且其中所述第二半导体区域设置在所述第一半导体区域的外部，并且其结深度为 基本上恒定的绝缘体，以及形成为覆盖第一半导体区域的一部分并与栅电极的侧面接触的绝缘体。

公开(公告)号：US07427544B2

公开(公告)日：2008-09-23

申请号：US11635761

申请日：2006-12-08

申请人： Amane Oishi

发明人： Amane Oishi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/4763

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/7843

摘要： A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stopper film formed on the gate electrode and first element region to cover the first element region and giving a tensile stress, a second stopper film formed on the gate electrode and second element region to cover the second element region and giving a compressive stress, and a contact connected to the gate electrode on the element isolation insulating film. The first and second stopper films overlap each other at least partially on the element isolation insulating film, and a total thickness of the first and second stopper films on the gate electrode on the element isolation insulating film is smaller than a total thickness outside the gate electrode.

摘要翻译： 半导体器件包括设置在第一和第二元件区域之间的半导体衬底中的元件隔离绝缘膜，在元件隔离绝缘膜上延伸的栅电极，第一和第二元件区域，形成在栅电极和第一元件上的第一阻挡膜 区域以覆盖第一元件区域并产生拉伸应力;形成在栅极电极和第二元件区域上以覆盖第二元件区域并产生压缩应力的第二阻挡膜，以及连接到元件隔离件上的栅电极的触点 绝缘膜。 第一和第二阻挡膜至少部分地彼此重叠在元件隔离绝缘膜上，并且元件隔离绝缘膜上的栅电极上的第一和第二阻挡膜的总厚度小于栅电极外的总厚度 。

公开(公告)号：US20070034953A1

公开(公告)日：2007-02-15

申请号：US11501236

申请日：2006-08-09

申请人： Amane Oishi

发明人： Amane Oishi

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/4908

摘要： A semiconductor device includes: a semiconductor substrate; a first transistor including a first gate electrode including a first metallic silicide layer, the first gate electrode being formed on the semiconductor substrate through a first gate insulating film, a first gate sidewall insulating film formed on a side face of the first gate electrode, and first impurity regions formed in the semiconductor substrate, the first gate electrode being formed between the first impurity regions; and a second transistor including a second gate electrode including a second metallic silicide layer, the second gate electrode being formed on the semiconductor substrate through a second gate insulating film, a second gate sidewall insulating film having a height, from the semiconductor substrate, lower than that of the first gate sidewall insulating film, the second gate sidewall insulating film being formed on a side face of the second gate electrode, and second impurity regions formed in the semiconductor substrate, the second gate electrode being formed between the second impurity regions.

摘要翻译： 半导体器件包括：半导体衬底; 第一晶体管，包括包括第一金属硅化物层的第一栅极电极，通过第一栅极绝缘膜在半导体衬底上形成第一栅电极，形成在第一栅电极的侧面上的第一栅极侧壁绝缘膜，以及 形成在所述半导体衬底中的第一杂质区，所述第一栅电极形成在所述第一杂质区之间; 以及第二晶体管，包括包括第二金属硅化物层的第二栅电极，所述第二栅极通过第二栅极绝缘膜形成在所述半导体衬底上，所述第二栅极侧壁绝缘膜具有从所述半导体衬底的高度低于 第一栅极侧壁绝缘膜，第二栅极侧壁绝缘膜形成在第二栅电极的侧面上，第二杂质区形成在半导体衬底中，第二栅电极形成在第二杂质区之间。

公开(公告)号：US08809077B2

公开(公告)日：2014-08-19

申请号：US13421320

申请日：2012-03-15

申请人： Amane Oishi

发明人： Amane Oishi

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/14 ,  H01L21/823418 ,  H01L22/20 ,  H01L29/665 ,  H01L29/7833

摘要： In a method of manufacturing of a semiconductor device according to an embodiment, an inspection transistor is subjected to silicidation and subsequently a characteristic of the inspection transistor is measured after the inspection transistor and a product transistor on a substrate are subjected to an annealing process. Thereafter, based on the measured characteristic, a characteristic adjustment annealing process to make a characteristic of the product transistor close to a desired characteristic is performed, and then the product transistor is subjected to silicidation.

摘要翻译： 在根据实施例的半导体器件的制造方法中，检查晶体管进行硅化，随后在检查晶体管之后测量检查晶体管的特性，并对基板上的商品晶体管进行退火处理。 然后，基于测定的特性，进行使产品晶体管的特性接近期望特性的特性调整退火处理，然后使产物晶体管进行硅化。

公开(公告)号：US07915688B2

公开(公告)日：2011-03-29

申请号：US12390840

申请日：2009-02-23

申请人： Amane Oishi

发明人： Amane Oishi

IPC分类号： H01L29/76

CPC分类号： H01L21/823425 ,  H01L21/28061 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor region via gate insulation films, an insulation film provided on the group of transistors, and a first contact layer and a second contact layer extending in the first direction and provided on the semiconductor region at opposite sides of the group of transistors.

摘要翻译： 半导体器件包括衬底，设置在衬底中的半导体区域，包括多个MIS晶体管的晶体管组，设置在半导体区域中，MIS晶体管包括沿第一方向延伸的多个栅电极， 在半导体区域上经由栅极绝缘膜，设置在晶体管组上的绝缘膜，以及在第一方向上延伸并设置在晶体管组的相对侧的半导体区域上的第一接触层和第二接触层。

公开(公告)号：US07514756B2

公开(公告)日：2009-04-07

申请号：US11482120

申请日：2006-07-07

申请人： Amane Oishi

发明人： Amane Oishi

IPC分类号： H01L29/76

CPC分类号： H01L21/823425 ,  H01L21/28061 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor region via gate insulation films, an insulation film provided on the group of transistors, and a first contact layer and a second contact layer extending in the first direction and provided on the semiconductor region at opposite sides of the group of transistors.

摘要翻译： 半导体器件包括衬底，设置在衬底中的半导体区域，包括多个MIS晶体管的晶体管组，设置在半导体区域中，MIS晶体管包括沿第一方向延伸的多个栅电极， 在半导体区域上经由栅极绝缘膜，设置在晶体管组上的绝缘膜，以及在第一方向上延伸并设置在晶体管组的相对侧的半导体区域上的第一接触层和第二接触层。

公开(公告)号：US07705417B2

公开(公告)日：2010-04-27

申请号：US11882083

申请日：2007-07-30

申请人： Amane Oishi

发明人： Amane Oishi

IPC分类号： H01L27/088

CPC分类号： H01L21/823807 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/7833 ,  H01L29/7846

摘要： A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation region including a liner film formed so as to contact a lower surface and a lower side surface of an inner wall of a trench formed in the semiconductor substrate, a first insulating film formed so that at least a part of a side surface and a lower surface of the first insulating film contact the liner film within the trench, and a second insulating film formed so as to contact an upper side of the first insulating film and formed so as to contact an upper side surface of the inner wall of the trench, the second insulating film having a higher etching resistance than that of the first insulating film; and a plurality of semiconductor elements disposed on the semiconductor substrate so as to be isolated from one another by the isolation region.

摘要翻译： 根据本发明实施例的半导体器件包括：半导体衬底; 隔离区域，包括形成为与所述半导体衬底中形成的沟槽的内壁的下表面和下侧表面接触的衬垫膜;第一绝缘膜，其形成为使得至少一部分侧表面和 所述第一绝缘膜的下表面与所述沟槽内的衬垫膜接触，并且形成为与所述第一绝缘膜的上侧接触并形成为与所述沟槽的内壁的上侧面接触的第二绝缘膜 所述第二绝缘膜具有比所述第一绝缘膜高的耐蚀刻性; 以及设置在半导体衬底上以便通过隔离区彼此隔离的多个半导体元件。

公开(公告)号：US20070108471A1

公开(公告)日：2007-05-17

申请号：US11482120

申请日：2006-07-07

申请人： Amane Oishi

发明人： Amane Oishi

IPC分类号： H01L31/00

CPC分类号： H01L21/823425 ,  H01L21/28061 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor region via gate insulation films, an insulation film provided on the group of transistors, and a first contact layer and a second contact layer extending in the first direction and provided on the semiconductor region at opposite sides of the group of transistors.

摘要翻译： 半导体器件包括衬底，设置在衬底中的半导体区域，包括多个MIS晶体管的晶体管组，设置在半导体区域中，MIS晶体管包括沿第一方向延伸的多个栅电极， 在半导体区域上经由栅极绝缘膜，设置在晶体管组上的绝缘膜，以及在第一方向上延伸并设置在晶体管组的相对侧的半导体区域上的第一接触层和第二接触层。