公开(公告)号：US20160379588A1

公开(公告)日：2016-12-29

申请号：US14995690

申请日：2016-01-14

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SUNG-JUN KIM ,  YONG-JAE LEE ,  KYUNG-HWA LIM ,  Kl-HYUN PYUN

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G3/3688 ,  G09G5/008 ,  G09G2310/08 ,  G09G2320/02

Abstract: A display panel driving apparatus includes a control circuit, a data driver and a gate driver. The control circuit is configured to receive a first control signal for recovering a clock signal from a display signal including image data and the clock signal, and calculate a root mean square of the first control signal to output a second control signal. The data driver is configured to receive the display signal, receive the second control signal, recover the clock signal from the display signal according to the second control signal, and output a data signal based on the image data to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel.

Abstract translation: 显示面板驱动装置包括控制电路，数据驱动器和门驱动器。 控制电路被配置为从包括图像数据和时钟信号的显示信号接收用于恢复时钟信号的第一控制信号，并且计算第一控制信号的均方根以输出第二控制信号。 数据驱动器被配置为接收显示信号，接收第二控制信号，根据第二控制信号从显示信号恢复时钟信号，并将基于图像数据的数据信号输出到显示面板的数据线 。 栅极驱动部件被配置为将栅极信号输出到显示面板的栅极线。

公开(公告)号：US20160027387A1

公开(公告)日：2016-01-28

申请号：US14563200

申请日：2014-12-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： MIN-YOUNG PARK ,  JEON-DOO LEE ,  SUNG-JUN KIM ,  YUN-MI KIM ,  KYUNG-HWA LIM ,  KI-HYUN PYUN

IPC: G09G3/34 ,  G09G3/36

CPC classification number: G09G3/3614 ,  G09G3/3611 ,  G09G2310/08 ,  G09G2320/0233

Abstract: A display device includes a display panel, a variable gate clock generator and a gate driver. The display panel includes a plurality of pixels coupled to a plurality of data lines and a plurality of gate lines, respectively. The variable gate clock generator generates a first variable gate clock signal and a second variable gate clock signal having respective duty ratios that are varied depending on a brightness of a frame image. The gate driver generates a plurality of gate driving signals for driving the gate lines in response to the first and second variable gate clock signals.

Abstract translation: 显示装置包括显示面板，可变门时钟发生器和栅极驱动器。 显示面板包括分别耦合到多条数据线和多条栅极线的多个像素。 可变门时钟发生器产生第一可变门时钟信号和具有根据帧图像的亮度而变化的各占空比的第二可变门时钟信号。 栅极驱动器响应于第一和第二可变栅极时钟信号产生用于驱动栅极线的多个栅极驱动信号。

公开(公告)号：US20190057667A1

公开(公告)日：2019-02-21

申请号：US15981239

申请日：2018-05-16

Applicant: Samsung Display Co, Ltd

Inventor： KIHYUN PYUN ,  YUNMI KIM ,  SUNG-JUN KIM ,  JUHYUN KIM ,  MINYOUNG PARK ,  HEEBUM PARK

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3677 ,  G09G2300/0857 ,  G09G2310/0243 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2310/0294 ,  G09G2310/08 ,  G09G2320/02 ,  G09G2330/02 ,  G09G2330/08 ,  G09G2370/08

Abstract: A display panel driver includes a timing controller and a data driver. The timing controller generates a data signal based on an input image data. The data driver receives the data signal, converts the data signal into a data voltage and outputs the data voltage to a display panel. The data signal includes positive data and negative data. The data driver includes a data skew compensating circuit which samples the positive data using the negative data and compensates a skew of the data signal.

公开(公告)号：US20170148397A1

公开(公告)日：2017-05-25

申请号：US15179080

申请日：2016-06-10

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： WOONYONG LIM ,  KYEONGSEOK LEE ,  JAEHYUN KOH ,  SUNG-JUN KIM ,  JEONG-HYUN KIM ,  SUNGSOO CHOI

IPC: G09G3/36

CPC classification number: G09G3/3607 ,  G09G3/3611 ,  G09G3/3614 ,  G09G3/3685 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0242

Abstract: A display apparatus includes a display panel, a timing controller and a data driver. The display panel includes a data line and first and second pixels connected to the data line. The timing controller generates a data signal and a data kickback control signal in response to input image data. The data driver generates first and second data voltages in response to the data signal, generates a data kickback signal in response to the data kickback control signal, processes the data voltages and the data kickback signal, and outputs the first data voltage to the data line during a first duration, the second data voltage to the data line during a second duration, and a first kickback data voltage to the data line during a first data kickback duration. The first data kickback duration is between the first and second durations.