DISPLAY DEVICE
    1.
    发明申请

    公开(公告)号:US20210319733A1

    公开(公告)日:2021-10-14

    申请号:US17118188

    申请日:2020-12-10

    IPC分类号: G09G3/00 G09G5/06

    摘要: A display device includes: a plurality of pixels; a first pixel unit comprising a first portion of the plurality of pixels; a second pixel unit comprising a second portion of the plurality of pixels; and a data driver configured to supply a data voltage to the first pixel unit and the second pixel unit, wherein the data driver is configured to generate a data voltage to be supplied to the first pixel unit based on different gamma voltages even when the same grayscale is expressed according to a driving method, and the second pixel unit is configured to be driven or not driven according to the driving method.

    DISPLAY DEVICE AND DRIVING METHOD THEREOF
    2.
    发明申请
    DISPLAY DEVICE AND DRIVING METHOD THEREOF 审中-公开
    显示装置及其驱动方法

    公开(公告)号:US20170047000A1

    公开(公告)日:2017-02-16

    申请号:US15156454

    申请日:2016-05-17

    IPC分类号: G09G3/20

    摘要: A display device includes a scan driver to supply a scan signal to scan lines, a data converter to receive a first data corresponding to a first wavelength range and to generate a second data corresponding to a second wavelength range by using the first data, a data driver to generate a data signal to be supplied to data lines by using the first data or the second data, and pixels in areas defined by the scan and data lines to emit light in accordance with the data signal.

    摘要翻译: 显示装置包括扫描驱动器,用于向扫描线提供扫描信号;数据转换器,用于接收对应于第一波长范围的第一数据,并通过使用第一数据产生对应于第二波长范围的第二数据;数据 驱动器,以通过使用第一数据或第二数据产生要提供给数据线的数据信号,并且由扫描和数据线定义的区域中的像素根据数据信号发光。

    SCAN DRIVER AND DISPLAY DEVICE
    4.
    发明公开

    公开(公告)号:US20230260464A1

    公开(公告)日:2023-08-17

    申请号:US18306211

    申请日:2023-04-24

    IPC分类号: G09G3/3266 G09G3/3275

    摘要: A scan driver includes: a plurality of stages, each stage including: a logic circuit configured to transfer an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal that is provided as the input signal for a next stage in response to a voltage of the bootstrapped first node; and a masking controller configured to receive a masking signal and the carry signal, and to output the masking signal as a scan signal provided to a pixel row corresponding to the each stage in response to the carry signal.

    DISPLAY DEVICE
    5.
    发明申请

    公开(公告)号:US20220123045A1

    公开(公告)日:2022-04-21

    申请号:US17501945

    申请日:2021-10-14

    发明人: Seong Heon CHO

    IPC分类号: H01L27/15 G09G3/32

    摘要: A display device includes a first display panel; and a second display panel, wherein the first display panel includes a first substrate including a first region and a second region that is thinner than the first region, a first scan driver positioned on one edge of the first region, a second scan driver positioned in the second region, and a plurality of pixels connected to the first scan driver and the second scan driver by a scan line, the second display panel includes a second substrate including a first region and a second region that is thinner than the first region, a first scan driver positioned on one edge of the first region, and a plurality of pixels connected to the first scan driver by a scan line.

    SCAN DRIVER AND DISPLAY DEVICE
    6.
    发明申请

    公开(公告)号:US20220165218A1

    公开(公告)日:2022-05-26

    申请号:US17666425

    申请日:2022-02-07

    IPC分类号: G09G3/3266 G09G3/3275

    摘要: A scan driver includes: a plurality of stages, each stage including: a logic circuit configured to transfer an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal that is provided as the input signal for a next stage in response to a voltage of the bootstrapped first node; and a masking controller configured to receive a masking signal and the carry signal, and to output the masking signal as a scan signal provided to a pixel row corresponding to the each stage in response to the carry signal.

    SCAN DRIVER AND DISPLAY DEVICE
    7.
    发明申请

    公开(公告)号:US20210110774A1

    公开(公告)日:2021-04-15

    申请号:US16888465

    申请日:2020-05-29

    IPC分类号: G09G3/3266 G09G3/3275

    摘要: A scan driver includes: a plurality of stages, each stage including: a logic circuit configured to transfer an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal that is provided as the input signal for a next stage in response to a voltage of the bootstrapped first node; and a masking controller configured to receive a masking signal and the carry signal, and to output the masking signal as a scan signal provided to a pixel row corresponding to the each stage in response to the carry signal.

    DISPLAY DEVICE AND DRIVING METHOD THEREOF

    公开(公告)号:US20210027719A1

    公开(公告)日:2021-01-28

    申请号:US16817403

    申请日:2020-03-12

    IPC分类号: G09G3/3291 G09G3/3258

    摘要: A display device and a driving method thereof are provided. The display device includes a display including a pixel including a double gate transistor and a light emitting diode, a power supply for supplying power to the display, a current sensor for sensing a current flowing in the display or in the light emitting diode, and a gate voltage controller for providing a bias voltage signal to one gate electrode of the double gate transistor.

    SHORT CIRCUIT DETECTOR AND DISPLAY DEVICE HAVING THE SAME

    公开(公告)号:US20190213936A1

    公开(公告)日:2019-07-11

    申请号:US16238518

    申请日:2019-01-03

    发明人: Seong Heon CHO

    IPC分类号: G09G3/00 H01L27/12 G01R31/02

    摘要: A short circuit detector includes a first transistor connected between a first portion of a data line and a second portion of the data line and including a gate electrode connected to a first node; a second transistor connected between a first voltage source and the first node and including a gate electrode configured to receive a short-circuit test signal; a third transistor connected between a second node included in the second portion and a third node and including a gate electrode configured to receive the short-circuit test signal; a fourth transistor connected between a second voltage source and the first node and including a gate electrode connected to the third node; and a fifth transistor connected to the first node and a third voltage source and including a gate electrode connected to the third node in common with the gate electrode of the third transistor.