THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    2.
    发明公开

    公开(公告)号:US20240203944A1

    公开(公告)日:2024-06-20

    申请号:US18370650

    申请日:2023-09-20

    CPC classification number: H01L25/0657 H01L2225/06513 H01L2225/06541

    Abstract: A semiconductor device includes a first die including a plurality of first micro bumps on a first upper face of the first die, a plurality of first macro metal pads at positions respectively corresponding to the plurality of first micro bumps, a first routing wiring layer comprising a plurality of first routing metals, where a first end of each of the plurality of first routing metals is respectively under the plurality of first macro metal pads, a plurality of through silicon vias (TSVs), where first ends of the plurality of TSVs are respectively connected to second ends of the plurality of first routing metals, and where each of the plurality of TSVs extends downward from the respective second ends of the plurality of first routing metals, a first plurality of keep-out zones including a first keep-out zone bundle region, and a plurality of first micro metal pads.

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