公开(公告)号：US20150039547A1

公开(公告)日：2015-02-05

申请号：US14328359

申请日：2014-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwan KANG ,  Kyung-chang RYOO ,  Hyun Goo JUN ,  Hongsik JEONG ,  JaeHee OH

IPC: G06N3/04

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: A method of generating neuron spiking pulses in a neuromorphic system is provided which includes floating one or more selected bit lines connected to target cells, having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; and stepwisely increasing voltages applied to unselected word lines connected to unselected cells, having a second state, from among memory cells connected to the one or more selected bit lines other than the target cells having the first state.

Abstract translation: 提供了一种在神经形态系统中产生神经元尖峰脉冲的方法，其包括从布置在多个字线的交叉点处的多个存储器单元中浮动连接到具有第一状态的目标单元的一个或多个选定位线， 多个位线; 以及从连接到除了具有第一状态的目标单元之外的所述一个或多个选定位线的存储单元之间逐步增加施加到连接到具有第二状态的未选择单元的未选择单元的电压的电压。

公开(公告)号：US20210384427A1

公开(公告)日：2021-12-09

申请号：US17143493

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilmok PARK ,  Kyusul PARK ,  Daehwan KANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A three-dimensional semiconductor memory device may include a first conductive line extending in a first direction, a second conductive line extending in a second direction crossing the first direction, a cell stack at an intersection of the first and second conductive lines, and a gapfill insulating pattern covering a side surface of the cell stack. The cell stack may include first, second, and third electrodes sequentially stacked, a switching pattern between the first and second electrodes, and a variable resistance pattern between the second and third electrodes. A top surface of the gapfill insulating pattern may be located between top and bottom surfaces of the third electrode.

公开(公告)号：US20220310698A1

公开(公告)日：2022-09-29

申请号：US17526262

申请日：2021-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmog PARK ,  Jungyu LEE ,  Daehwan KANG ,  Sungho EUN

IPC: H01L27/24

Abstract: A resistive memory device includes: memory cells overlapping one another in a vertical direction within a cell array region and each including a switching element and a variable resistive element; first conductive lines each being connected to the switching element; a second conductive line connected to the variable resistive element and conductive pads arranged in a connection region and connected to respective one ends of the first conductive lines, respectively, and having different lengths in the second horizontal direction. A lower conductive pad from among the conductive pads includes a first portion covered by an upper conductive pad, and a second portion not covered by the upper conductive pad, and a thickness of each of the first and second portions in the vertical direction is greater than a thickness of each of the first conductive lines in the vertical direction.