公开(公告)号：US20210167130A1

公开(公告)日：2021-06-03

申请号：US16937963

申请日：2020-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyusul PARK ,  Woohyun PARK ,  Ilmok PARK ,  Seulji Song

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device and a method of fabricating a variable resistance memory device, the device including first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells at respective intersection points of the first conductive lines and the second conductive lines, wherein each of the memory cells includes a switching pattern, an intermediate electrode, a variable resistance pattern, and an upper electrode, which are between the first and second conductive lines and are connected in series; and a spacer structure including a first spacer and a second spacer, the first spacer being on a side surface of the upper electrode, and the second spacer covering the first spacer and a side surface of the variable resistance pattern such that the second spacer is in contact with the side surface of the variable resistance pattern.

公开(公告)号：US20200075854A1

公开(公告)日：2020-03-05

申请号：US16426216

申请日：2019-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilmok PARK ,  Kyusul PARK ,  Seulji SONG ,  Kwang-Woo LEE

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.

公开(公告)号：US20210384427A1

公开(公告)日：2021-12-09

申请号：US17143493

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilmok PARK ,  Kyusul PARK ,  Daehwan KANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A three-dimensional semiconductor memory device may include a first conductive line extending in a first direction, a second conductive line extending in a second direction crossing the first direction, a cell stack at an intersection of the first and second conductive lines, and a gapfill insulating pattern covering a side surface of the cell stack. The cell stack may include first, second, and third electrodes sequentially stacked, a switching pattern between the first and second electrodes, and a variable resistance pattern between the second and third electrodes. A top surface of the gapfill insulating pattern may be located between top and bottom surfaces of the third electrode.

公开(公告)号：US20210134884A1

公开(公告)日：2021-05-06

申请号：US17088168

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Ilmok PARK ,  Junhee LIM

IPC: H01L27/24 ,  H01L27/1157 ,  G11C11/16 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/11575 ,  G11C14/00 ,  G11C5/02 ,  G11C16/04

Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.