公开(公告)号：US09792974B2

公开(公告)日：2017-10-17

申请号：US14966039

申请日：2015-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewoong Ha ,  Byungchul Ko ,  Daekyoung Kim ,  Jonghwan Kim

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C7/1045 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2211/4067

Abstract: A memory system including a plurality of dynamic random access memory (DRAM) devices and a DRAM controller is provided. The plurality of DRAM devices includes one or more DRAM groups. Each of the one or more DRAM groups includes at least two DRAM devices. The DRAM controller outputs a clock enable signal, and controls a selection signal used to select a target DRAM device that operates in a normal mode in response to the clock enable signal. At least one target DRAM device is selected from the one or more DRAM groups. One or more stand-by DRAM devices other than the at least one target DRAM device operates in a self-refresh mode.

公开(公告)号：US11119692B2

公开(公告)日：2021-09-14

申请号：US16510029

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonwu Kim ,  Daekyoung Kim ,  Seok-Won Ahn ,  Chanho Yoon

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/08 ,  G11C16/04

Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

公开(公告)号：US20200150893A1

公开(公告)日：2020-05-14

申请号：US16510029

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonwu Kim ,  Daekyoung Kim ,  Seok-Won Ahn ,  Chanho Yoon

IPC: G06F3/06 ,  G11C16/32

Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.