公开(公告)号：US20240136813A1

公开(公告)日：2024-04-25

申请号：US18227599

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukjin KIM ,  Sangyoung CHO ,  Eonguk KIM ,  Chanhee JEON

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.

公开(公告)号：US20130335127A1

公开(公告)日：2013-12-19

申请号：US13755521

申请日：2013-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eonguk KIM

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008

Abstract: An apparatus for controlling retention of data includes a logic circuit, a retention control cell circuit, and an I/O cell circuit. The logic circuit generates at least one retention enable signal before a chip enters a reduced power mode. The retention control cell circuit latches the retention enable signal and outputs a retention enable control signal based on a first power signal of the logic circuit and a detection result of a second power signal for input/output (I/O). And, the I/O cell circuit latches data based on the retention control signal.

Abstract translation: 用于控制数据保持的装置包括逻辑电路，保持控制单元电路和I / O单元电路。 在芯片进入降低功率模式之前，逻辑电路产生至少一个保持使能信号。 保持控制单元电路锁存保持使能信号，并基于逻辑电路的第一功率信号和用于输入/输出（I / O）的第二功率信号的检测结果输出保持使能控制信号。 并且，I / O单元电路基于保持控制信号来锁存数据。

公开(公告)号：US20240235189A9

公开(公告)日：2024-07-11

申请号：US18227599

申请日：2023-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukjin KIM ,  Sangyoung CHO ,  Eonguk KIM ,  Chanhee JEON

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.

公开(公告)号：US20230082252A1

公开(公告)日：2023-03-16

申请号：US17890509

申请日：2022-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eonguk KIM

IPC: H03K17/687

Abstract: An output driving circuit includes: a plurality of bias voltage generating circuits configured to generate a plurality of bias voltages; a switching control circuit; and an output voltage generating circuit. The switching control circuit is configured to selectively connect one bias voltage generating circuit of the plurality of bias voltage generating circuits to the output voltage generating circuit based on an output voltage. The output voltage generating circuit is configured to transmit and receive a parasitic current generated due to transition of the output voltage to and from the one bias voltage generating circuit selectively connected to the output voltage generating circuit through the switching control circuit.

公开(公告)号：US20140354337A1

公开(公告)日：2014-12-04

申请号：US14461815

申请日：2014-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eonguk KIM

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008

Abstract: An apparatus for controlling retention of data includes a logic circuit, a retention control cell circuit, and an I/O cell circuit. The logic circuit generates at least one retention enable signal before a chip enters a reduced power mode. The retention control cell circuit latches the retention enable signal and outputs a retention enable control signal based on a first power signal of the logic circuit and a detection result of a second power signal for inputoutput (I/O). And, the I/O cell circuit latches data based on the retention control signal.

Abstract translation: 用于控制数据保持的装置包括逻辑电路，保持控制单元电路和I / O单元电路。 在芯片进入降低功率模式之前，逻辑电路产生至少一个保持使能信号。 保持控制单元电路锁存保持使能信号，并且基于逻辑电路的第一功率信号和用于输入输出（I / O）的第二功率信号的检测结果输出保持使能控制信号。 并且，I / O单元电路基于保持控制信号来锁存数据。