公开(公告)号：US20240136813A1

公开(公告)日：2024-04-25

申请号：US18227599

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukjin KIM ,  Sangyoung CHO ,  Eonguk KIM ,  Chanhee JEON

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.

公开(公告)号：US20240282764A1

公开(公告)日：2024-08-22

申请号：US18443892

申请日：2024-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyukhoon KWON ,  Chanhee JEON ,  Kyoungil DO ,  Mijin LEE

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0288 ,  H02H9/046

Abstract: Provided is a device including a first well having a first conductivity type, a first gate electrode on the first well, a first region and a second region each having a second conductivity type on the first well with the first gate electrode disposed therebetween, a third region having the second conductivity type on the first well, and a fourth region having the first conductivity type on the first well. The first gate electrode and the first region are electrically connected to a first node, and the third region is electrically connected to a second node.

公开(公告)号：US20240145463A1

公开(公告)日：2024-05-02

申请号：US18384677

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungil DO ,  Jinwoo JUNG ,  Jooyoung SONG ,  Mijin LEE ,  Chanhee JEON

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7408

Abstract: A device including a silicon controlled rectifier including an anode and a cathode; at least one first transistor connected between the anode and a gate of the silicon controlled rectifier; and a second transistor including a source connected to one from among the cathode or the anode, and a drain connected to a body of the at least one first transistor.

公开(公告)号：US20240413631A1

公开(公告)日：2024-12-12

申请号：US18733208

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungil DO ,  Chanhee JEON ,  Jooyoung SONG ,  Jinwoo JUNG

IPC: H02H9/04 ,  H01L27/02 ,  H03K17/60 ,  H03K17/687

Abstract: A device includes: a first silicon-controlled rectifier comprising a first PNP bipolar junction transistor (BJT) and a first NPN BJT in which bases and collectors are cross-coupled; and a field effect transistor (FET) configured to, based on an electrostatic discharge occurring between an anode of the first silicon-controlled rectifier and a cathode of the first silicon-controlled rectifier, trigger the first silicon-controlled rectifier. An emitter of the first PNP BJT corresponds to a plurality of first p+ regions being spaced apart from each other in a first direction. The FET is connected to the first silicon-controlled rectifier through at least one first n+ region disposed between the plurality of first p+ regions.

公开(公告)号：US20240235189A9

公开(公告)日：2024-07-11

申请号：US18227599

申请日：2023-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukjin KIM ,  Sangyoung CHO ,  Eonguk KIM ,  Chanhee JEON

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.