公开(公告)号：US10424571B2

公开(公告)日：2019-09-24

申请号：US15696973

申请日：2017-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Choi ,  Eun-Seok Song ,  Seung-Yong Cha ,  Yun-Hee Lee

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01F27/28 ,  H01F27/24 ,  H01L25/065 ,  H01F17/00 ,  H01L23/00

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

公开(公告)号：US20190057949A1

公开(公告)日：2019-02-21

申请号：US15868411

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Joo Hwang ,  Eun-Seok Song

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L49/02 ,  H01L23/31

Abstract: A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer.

公开(公告)号：US11244938B2

公开(公告)日：2022-02-08

申请号：US16554818

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Choi ,  Eun-Seok Song ,  Seung-Yong Cha ,  Yun-Hee Lee

IPC: H01L25/18 ,  H01L23/538 ,  H01F27/28 ,  H01F27/24 ,  H01L25/065 ,  H01F17/00 ,  H01L23/498 ,  H01L23/00

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

公开(公告)号：US10262967B2

公开(公告)日：2019-04-16

申请号：US15868411

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Joo Hwang ,  Eun-Seok Song

IPC: H01L23/485 ,  H01L21/02 ,  H01L25/10 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02 ,  H01L23/31

Abstract: A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer.

公开(公告)号：US09893020B2

公开(公告)日：2018-02-13

申请号：US15227953

申请日：2016-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-Woo Lee ,  Eun-Seok Song ,  Young-Jae Kim ,  Jae-Gwon Jang

IPC: H01L43/02 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: In one embodiment, a semiconductor device comprising, a substrate comprising a wiring layer, a first conductive shielding layer disposed on the substrate and electrically isolated from the wiring layer, the first conductive shielding layer comprising a first bonding surface and a first end surface extending from the first bonding surface, a semiconductor chip disposed on the first conductive shielding layer, a molding member disposed over the first conductive shielding layer to cover the semiconductor chip, a second conductive shielding layer disposed over the first conductive shielding layer and the molding member, the second conductive shielding layer comprising a second bonding surface and a second end surface extending from the second bonding surface, and a bonding portion disposed between the first and second bonding surfaces, the bonding portion comprising a top surface and a bottom surface opposite to the top surface. The bottom surface of the bonding portion contacts the first bonding surface to form a first contact surface. The top surface of the bonding portion contacts the second bonding surface to form a second contact surface. An area of the second contact surface is larger than an area of the second end surface.