公开(公告)号：US20240274212A1

公开(公告)日：2024-08-15

申请号：US18241621

申请日：2023-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yumin KIM ,  Jungyu LEE ,  Jihyun PARK ,  Chiweon YOON ,  Eunchan LEE

IPC: G11C29/12 ,  G11C7/04 ,  G11C29/02

CPC classification number: G11C29/12005 ,  G11C7/04 ,  G11C29/028 ,  G11C29/1201

Abstract: A voltage generation circuit includes a current generation circuit, a slope trimming circuit and an offset trimming circuit. The current generation circuit is connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases. The current generation circuit generates a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature. The slope trimming circuit is connected between the output node and an intermediate node. The slope trimming circuit adjusts a slope of the CTAT output voltage based on a first trimming code. The offset trimming circuit is connected between the intermediate node and a ground voltage node. The offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.

公开(公告)号：US20240257843A1

公开(公告)日：2024-08-01

申请号：US18230951

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jihyun PARK ,  Jungyu LEE ,  Yumin KIM ,  Chiweon YOON ,  Eunchan LEE

IPC: G11C7/02 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/02 ,  G11C7/1057 ,  G11C7/14

Abstract: The present disclosure provides for memory apparatuses and systems including noise cancellation circuits, and operating methods thereof. In some embodiments, a memory device includes a first pad, a memory cell plane comprising a plurality of memory cells, a page buffer circuit, and a noise cancellation circuit. The page buffer circuit is configured to sense the memory cell plane, and identify, based on the sensing of the memory cell plane, a state stored in a memory cell of the plurality of memory cells, according to a ground voltage. The noise cancellation circuit is configured to receive a first ground voltage from the first pad, determine a reference voltage based on the first ground voltage, generate a second ground voltage that offsets a noise voltage, based on the reference voltage, and output the second ground voltage to the page buffer circuit.