公开(公告)号：US20240257843A1

公开(公告)日：2024-08-01

申请号：US18230951

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jihyun PARK ,  Jungyu LEE ,  Yumin KIM ,  Chiweon YOON ,  Eunchan LEE

IPC: G11C7/02 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/02 ,  G11C7/1057 ,  G11C7/14

Abstract: The present disclosure provides for memory apparatuses and systems including noise cancellation circuits, and operating methods thereof. In some embodiments, a memory device includes a first pad, a memory cell plane comprising a plurality of memory cells, a page buffer circuit, and a noise cancellation circuit. The page buffer circuit is configured to sense the memory cell plane, and identify, based on the sensing of the memory cell plane, a state stored in a memory cell of the plurality of memory cells, according to a ground voltage. The noise cancellation circuit is configured to receive a first ground voltage from the first pad, determine a reference voltage based on the first ground voltage, generate a second ground voltage that offsets a noise voltage, based on the reference voltage, and output the second ground voltage to the page buffer circuit.

公开(公告)号：US20240274212A1

公开(公告)日：2024-08-15

申请号：US18241621

申请日：2023-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yumin KIM ,  Jungyu LEE ,  Jihyun PARK ,  Chiweon YOON ,  Eunchan LEE

IPC: G11C29/12 ,  G11C7/04 ,  G11C29/02

CPC classification number: G11C29/12005 ,  G11C7/04 ,  G11C29/028 ,  G11C29/1201

Abstract: A voltage generation circuit includes a current generation circuit, a slope trimming circuit and an offset trimming circuit. The current generation circuit is connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases. The current generation circuit generates a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature. The slope trimming circuit is connected between the output node and an intermediate node. The slope trimming circuit adjusts a slope of the CTAT output voltage based on a first trimming code. The offset trimming circuit is connected between the intermediate node and a ground voltage node. The offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.

公开(公告)号：US20240105524A1

公开(公告)日：2024-03-28

申请号：US18367229

申请日：2023-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjin KIM ,  Minhwan SEO ,  Wondon JOO ,  Jiyoung CHU ,  Sangwoo BAE ,  Sungmin AHN ,  Seungyeol OH ,  Jungyu LEE

IPC: H01L21/66 ,  G02B5/30 ,  G02B27/09 ,  G02B27/28 ,  H01L21/68

CPC classification number: H01L22/12 ,  G02B5/3083 ,  G02B27/0955 ,  G02B27/0977 ,  G02B27/283 ,  H01L21/681

Abstract: The optical device includes an illuminator configured to emit illumination light in a first horizontal direction, a polarizing prism configured to polarize the illumination light incident thereto through a first surface thereof in the first horizontal direction, a first reflector and a second reflector, each configured to reflect the illumination light from the polarizing prism, and a first lens and a second lens configured to condense the illumination light reflected from the first and second reflectors, respectively.

公开(公告)号：US20240303153A1

公开(公告)日：2024-09-12

申请号：US18472682

申请日：2023-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hoan PARK ,  Yeon Soo KWON ,  Hancheon YUN ,  Jungyu LEE ,  Jaeseung JEONG

IPC: G06F11/07

CPC classification number: G06F11/0793

Abstract: An error correction circuit includes a clock delay circuit configured to receive an input clock, delay the input clock by a desired time period to generate a delayed clock, and output one of the input clock and the delayed clock as an output clock in response to a select signal, an error detection circuit configured to, receive the output clock and input data, generate output data and latch data based on the output clock and the input data, and detect a margin error based on the output data and the latch data, and a control circuit configured to correct the detected margin error, the correcting the margin error including adjusting a level of the select signal based on whether the margin error has been detected.

公开(公告)号：US20220310698A1

公开(公告)日：2022-09-29

申请号：US17526262

申请日：2021-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmog PARK ,  Jungyu LEE ,  Daehwan KANG ,  Sungho EUN

IPC: H01L27/24

Abstract: A resistive memory device includes: memory cells overlapping one another in a vertical direction within a cell array region and each including a switching element and a variable resistive element; first conductive lines each being connected to the switching element; a second conductive line connected to the variable resistive element and conductive pads arranged in a connection region and connected to respective one ends of the first conductive lines, respectively, and having different lengths in the second horizontal direction. A lower conductive pad from among the conductive pads includes a first portion covered by an upper conductive pad, and a second portion not covered by the upper conductive pad, and a thickness of each of the first and second portions in the vertical direction is greater than a thickness of each of the first conductive lines in the vertical direction.

公开(公告)号：US20210098064A1

公开(公告)日：2021-04-01

申请号：US16848149

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jungyu LEE ,  Bilal Ahmad JANJUA

IPC: G11C13/00

Abstract: A resistive memory device includes a memory cell array of resistive memory cells connected to word and bit lines, each bay of the memory cell array including K tiles; a write/read circuit connected to the memory cell array through a row decoder and a column decoder, the write/read circuit being configured to perform a write operation in a target tile of the memory cell array, the write/read circuit comprising write drivers corresponding to the bays; a control voltage generator configured to generate first and second control voltages based on a reference current; and a control circuit configured to control the write/read circuit and the control voltage generator. A first write driver that corresponds to a first bay of the bays is configured to provide the target tile with a write current corresponding to a physical position of a selected memory cell of the target tile in the memory cell array.