公开(公告)号：US10318469B2

公开(公告)日：2019-06-11

申请号：US14620219

申请日：2015-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Soo Jang ,  Gong-Heum Han ,  Chul-Sung Park ,  Jang-Woo Ryu ,  Chang-Yong Lee ,  Tae-Seong Jang

IPC: G06F13/36 ,  G06F13/42

Abstract: A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.

公开(公告)号：US09601172B2

公开(公告)日：2017-03-21

申请号：US14668232

申请日：2015-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Yong Lee ,  Gong-Heum Han

IPC: G11C8/00 ,  G11C8/18 ,  G11C8/06

CPC classification number: G11C8/18 ,  G11C8/06

Abstract: An address aligner includes a command address providing unit, an alignment signal providing unit and an alignment unit. The command address providing unit outputs a sync command address signal by delaying a command address signal in synchronization with a first clock signal. The sync command address signal is synchronized with the first clock signal. The alignment signal providing unit outputs alignment clock signals by delaying a chip select signal in synchronization with a second clock signal. The alignment clock signals are synchronized with the second clock signal. The alignment unit outputs a plurality of addresses in synchronization with the alignment clock signals. The plurality of addresses is included in the sync command address signal. If the address aligner according to example embodiments is used, the operation speed of the memory device may be increased by aligning a plurality of addresses in synchronization with the alignment clock signal that is generated based on a chip select signal.