公开(公告)号：US20240145021A1

公开(公告)日：2024-05-02

申请号：US18236177

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong KIM ,  Hyun-Jin Shin

IPC: G11C29/12 ,  G11C7/08 ,  G11C29/46

CPC classification number: G11C29/1201 ,  G11C7/08 ,  G11C29/46

Abstract: A flash memory includes a first memory cell connected with a selected word line and a first bit line, a second memory cell connected with the selected word line and a second bit line, a sense amplifier that provides a sensing line with a sensing current for sensing data stored in the first memory cell or the second memory cell, a bit line selection circuit that selects a bit line by connecting the sensing line with the first bit line or the second bit line, and a margin read test circuit that performs a margin read test operation in which the margin read test circuit provides the sensing line with a margin current for testing a read margin of the data stored in the first memory cell or the second memory cell that is connected to the selected bit line.