Abstract:
A nonvolatile memory device includes a memory cell array including a main memory area and a dummy memory area, a row decoder, a bit line selection circuit, a data input/output circuit, a control circuit, and a voltage generator. The bit line selection circuit is configured to select a first main bit line during a program time and is configured to select a dummy bit line during a column address switch time. During the column address switch time, a second main bit line is selected. The voltage generator is configured to output, to the row decoder, a source line voltage to be applied to a selected source line during the program time and during the column address switch time, wherein the source line voltage is maintained at a voltage level during the program time and during the column address switch time.
Abstract:
A nonvolatile memory device includes a memory cell array including a plurality of memory cells that are programmed based on a high voltage, a high voltage generator to generate the high voltage by boosting an input voltage based on a pumping clock, a pumping clock generator to generate the pumping clock, a high voltage detector to generate a detection signal by comparing an adjustment voltage with a reference voltage, a programming current controller to adjust a programming current flowing through each of selected memory cells of the plurality of memory cells; and a control logic to adjust a frequency of the pumping clock and a current driving capability of the programming current based on the detection signal during a programming period with respect to the selected memory cells. The detection signal includes information indicating whether the high voltage reaches to a target voltage.
Abstract:
A memory device includes a memory cell, a bit line connected to the memory cell, a control voltage generator configured to generate a proportional to absolute temperature (PTAT) current and generate an analog control voltage inversely proportional to the PTAT current, and a load current control circuit configured to control a first load current supplied to the bit line based on the analog control voltage.
Abstract:
A precharge control signal generator and a semiconductor memory device include a precharge control signal generating circuit which generates a precharge control signal and applies the precharge control signal to a sensing circuit, and a sensing circuit configured to precharge a bit line connected to a memory cell according to the precharge control signal and read data stored in the memory cell. The precharge control signal controls the sensing circuit so that a precharge time is adjusted according to operating temperature.
Abstract:
A non-volatile memory device is provided. The non-volatile memory device may include a memory cell array, a first pumping circuit configured to output a first pumping voltage, a second pumping circuit configured to pump the first pumping voltage of the first pumping circuit to output a second pumping voltage, and a pumping circuit control unit which is connected to the first pumping circuit and the second pumping circuit and configured to output at least one of the first pumping voltage and the second pumping voltage to the memory cell array. The first pumping circuit may be enabled in a first mode and a second mode different from the first mode, and the second pumping circuit may be disabled or not enabled in the first mode and enabled in the second mode.
Abstract:
A sensing circuit of nonvolatile memory device includes a precharge current generator, an adjusting transistor, and an adaptive control voltage generator. The precharge current generator connected to a sensing node and generates a precharge current provided to a bit-line of the nonvolatile memory device, in response to a precharge signal. The adjusting transistor, connected between the sensing node and a first node, adjusts an amount of the precharge current provided to the bit-line in response to a first control voltage. The adaptive control voltage generator generates a control current proportional to an operating temperature, in response to the precharge signal and a second control voltage and boosts a level of the first control voltage in proportion to the operating temperature. The second control voltage is inversely proportional to the operating temperature.
Abstract:
A precharge control signal generator and a semiconductor memory device include a precharge control signal generating circuit which generates a precharge control signal and applies the precharge control signal to a sensing circuit, and a sensing circuit configured to precharge a bit line connected to a memory cell according to the precharge control signal and read data stored in the memory cell. The precharge control signal controls the sensing circuit so that a precharge time is adjusted according to operating temperature.
Abstract:
Provided a voltage generating circuits including assist circuits and operating methods thereof. The voltage generating circuit which includes an assist circuit that generates an assist signal indicating an enable mode or a disable mode. When a first power supply voltage is lower than an assist reference voltage, the assist signal indicates the enable mode, and a compensation circuit generates a compensation signal based on the first power supply voltage. An internal voltage converter generates a regulated voltage based on the first power supply voltage, and a charge pump circuit generates a pump voltage based on the regulated voltage. The compensation signal compensates for the regulated voltage.
Abstract:
A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.
Abstract:
A semiconductor memory device includes a memory cell array including a plurality of memory cells connected to a plurality of bit lines, a control signal generating circuit configured to generate a first control signal in response to a first operating temperature of the semiconductor memory device and a second control signal in response to a second operating temperature of the semiconductor memory device, a precharge circuit configured to provide a precharge current to a first bit line of the plurality of bit lines in response to an enable signal, and a boost circuit configured to provide a boost current to the first bit line in response to the enable signal, wherein the magnitude of the boost circuit is responsive to one of the first and second control signals.