公开(公告)号：US12230630B2

公开(公告)日：2025-02-18

申请号：US17571954

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

公开(公告)号：US20240372002A1

公开(公告)日：2024-11-07

申请号：US18775240

申请日：2024-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung In Choi ,  Hae Jun Yu ,  Sung Hun Jung

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/08

Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.

公开(公告)号：US12080796B2

公开(公告)日：2024-09-03

申请号：US17462026

申请日：2021-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung In Choi ,  Hae Jun Yu ,  Sung Hun Jung

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L23/5283 ,  H01L29/0847

Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.

公开(公告)号：US20220399330A1

公开(公告)日：2022-12-15

申请号：US17571954

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.