公开(公告)号：US12230630B2

公开(公告)日：2025-02-18

申请号：US17571954

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

公开(公告)号：US10784379B2

公开(公告)日：2020-09-22

申请号：US15995414

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon Kim ,  Dong Myoung Kim ,  Dong Suk Shin ,  Seung Hun Lee ,  Cho Eun Lee ,  Hyun Jung Lee ,  Sung Uk Jang ,  Edward Nam Kyu Cho ,  Min-Hee Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L27/12

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US11728434B2

公开(公告)日：2023-08-15

申请号：US17011221

申请日：2020-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon Kim ,  Dong Myoung Kim ,  Dong Suk Shin ,  Seung Hun Lee ,  Cho Eun Lee ,  Hyun Jung Lee ,  Sung Uk Jang ,  Edward Nam Kyu Cho ,  Min-Hee Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L27/12

CPC classification number: H01L29/7855 ,  H01L21/02532 ,  H01L21/76871 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02645 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US20220399330A1

公开(公告)日：2022-12-15

申请号：US17571954

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.