公开(公告)号：US20230326848A1

公开(公告)日：2023-10-12

申请号：US18086340

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGJIN LEE ,  EUN-JI JUNG ,  Hobin JUNG ,  HYUN CHO

IPC: H01L23/522 ,  H01L27/092 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L23/5226 ,  H01L27/092 ,  H01L23/5283 ,  H01L23/53238 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/775

Abstract: Provided is a semiconductor device including a substrate including an active region, transistors on the substrate, a first interlayer insulating layer and a second interlayer insulating layer on the transistors, a first interconnection line in an upper portion of the first interlayer insulating layer, and a second interconnection line in the second interlayer insulating layer, wherein the first interconnection line includes a first barrier pattern, a first liner, and a first conductive pattern, wherein the second interconnection line includes a second barrier pattern, a second liner, and a second conductive pattern, wherein first height between an uppermost portion of a top surface of the first conductive pattern and a lowermost portion of a top surface of the first liner is greater than a second height between an uppermost portion of a top surface of the second conductive pattern and a lowermost portion of a top surface of the second liner.