公开(公告)号：US20220404859A1

公开(公告)日：2022-12-22

申请号：US17841078

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunil Kim ,  Jisu Kang ,  Taewook Park ,  Hongmook Choi

IPC: G06F1/10 ,  G06F1/12

Abstract: A clock generating circuit includes an oscillator, a clock counter, a finite state machine, and a non-volatile memory. The oscillator outputs an oscillator clock signal having a period based on a trim value. The clock counter counts the oscillator clock signal for a reference time. The finite state machine obtains the count value of the counted oscillator clock signal from the clock counter, and in a test mode, compares the count value with a target count value and changes the trim value based on the comparison result and determines a final trim value based on the changed trim value. The non-volatile memory stores the final trim value that is determined.

公开(公告)号：US12169419B2

公开(公告)日：2024-12-17

申请号：US17841078

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunil Kim ,  Jisu Kang ,  Taewook Park ,  Hongmook Choi

IPC: G06F1/10 ,  G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/56 ,  H03K21/38

Abstract: A clock generating circuit includes an oscillator, a clock counter, a finite state machine, and a non-volatile memory. The oscillator outputs an oscillator clock signal having a period based on a trim value. The clock counter counts the oscillator clock signal for a reference time. The finite state machine obtains the count value of the counted oscillator clock signal from the clock counter, and in a test mode, compares the count value with a target count value and changes the trim value based on the comparison result and determines a final trim value based on the changed trim value. The non-volatile memory stores the final trim value that is determined.

公开(公告)号：US11593527B2

公开(公告)日：2023-02-28

申请号：US17060099

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeok Kim ,  Hyesoo Lee ,  Hongmook Choi ,  Jisu Kang ,  Hyunil Kim ,  Jonghoon Shin

IPC: G06F21/72 ,  G06F21/78 ,  G06F21/60 ,  G11C8/10

Abstract: A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.

公开(公告)号：US20240356726A1

公开(公告)日：2024-10-24

申请号：US18634211

申请日：2024-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gapkyoung Kim ,  Jaehyeok Kim ,  Yongki Lee ,  Hongmook Choi

IPC: H04L9/06

CPC classification number: H04L9/0631

Abstract: An encryption device includes an encryption core circuit configured to generate output data by performing an encryption operation on input data, and an encryption controller circuit configured to control an operation of the encryption core. The encryption core circuit includes a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data, a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data, a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data, and a round key addition operation circuit configured to generate the output data by performing a round key addition operation on the first mid data.

公开(公告)号：US20210264061A1

公开(公告)日：2021-08-26

申请号：US17060099

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeok Kim ,  Hyesoo Lee ,  Hongmook Choi ,  Jisu Kang ,  Hyunil Kim ,  Jonghoon Shin

IPC: G06F21/72 ,  G11C8/10 ,  G06F21/60 ,  G06F21/78

Abstract: A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.