公开(公告)号：US11593527B2

公开(公告)日：2023-02-28

申请号：US17060099

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeok Kim ,  Hyesoo Lee ,  Hongmook Choi ,  Jisu Kang ,  Hyunil Kim ,  Jonghoon Shin

IPC: G06F21/72 ,  G06F21/78 ,  G06F21/60 ,  G11C8/10

Abstract: A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.

公开(公告)号：US11804276B2

公开(公告)日：2023-10-31

申请号：US17467861

申请日：2021-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhye Oh ,  Jaehyeok Kim ,  Yong Ki Lee ,  Gapkyoung Kim ,  Taewook Park

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/10 ,  G11C29/36

CPC classification number: G11C29/42 ,  G11C29/10 ,  G11C29/36 ,  G11C29/4401

Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.

公开(公告)号：US20210264061A1

公开(公告)日：2021-08-26

申请号：US17060099

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeok Kim ,  Hyesoo Lee ,  Hongmook Choi ,  Jisu Kang ,  Hyunil Kim ,  Jonghoon Shin

IPC: G06F21/72 ,  G11C8/10 ,  G06F21/60 ,  G06F21/78

Abstract: A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.

公开(公告)号：US20240356726A1

公开(公告)日：2024-10-24

申请号：US18634211

申请日：2024-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gapkyoung Kim ,  Jaehyeok Kim ,  Yongki Lee ,  Hongmook Choi

IPC: H04L9/06

CPC classification number: H04L9/0631

Abstract: An encryption device includes an encryption core circuit configured to generate output data by performing an encryption operation on input data, and an encryption controller circuit configured to control an operation of the encryption core. The encryption core circuit includes a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data, a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data, a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data, and a round key addition operation circuit configured to generate the output data by performing a round key addition operation on the first mid data.

公开(公告)号：US20240021261A1

公开(公告)日：2024-01-18

申请号：US18475968

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhye Oh ,  Jaehyeok Kim ,  Yong Ki Lee ,  Gapkyoung Kim ,  Taewook Park

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/10 ,  G11C29/36

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/10 ,  G11C29/36

Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.