公开(公告)号：US11514973B2

公开(公告)日：2022-11-29

申请号：US17003038

申请日：2020-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Rim ,  Yongho Kim ,  Hoonki Kim

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4097 ,  G11C11/4094 ,  G11C5/14 ,  G11C11/419 ,  G11C11/418 ,  G11C11/413 ,  G11C7/12 ,  G11C11/417 ,  G11C11/416

Abstract: A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interposed between the first word line and the n-th word line; bit lines; a first power node located adjacent to the first word line; a second power node located adjacent to the n-th word line; a first switch connected between the first power node and the cell array; a write driver located adjacent to the n-th word line and connected to the bit lines; and a switch controller configured to control the first switch to isolate the first power node from the memory cells during a write operation on memory cells connected to the first word line.

公开(公告)号：US10134486B2

公开(公告)日：2018-11-20

申请号：US15699412

申请日：2017-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonki Kim ,  Yongho Kim ,  Changnam Park ,  Taejoong Song ,  Woojin Rim ,  Jonghoon Jung

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/26 ,  G11C5/02

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.

公开(公告)号：US10049728B2

公开(公告)日：2018-08-14

申请号：US15611274

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonki Kim ,  Jonghoon Jung ,  Yongho Kim

IPC: G11C11/419

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.