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公开(公告)号：US20200220548A1
公开(公告)日：2020-07-09
申请号：US16820835
申请日：2020-03-17
发明人： Taejoong SONG , Jungho Do , Seungyoung Lee , Jonghoon Jung
IPC分类号： H03K19/17724 , H01L27/02 , H01L29/06 , H01L23/528 , H01L29/423 , H01L27/088
摘要： A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.
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公开(公告)号：US20190267366A1
公开(公告)日：2019-08-29
申请号：US16407919
申请日：2019-05-09
发明人： JUNG-HO DO , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L27/092 , H01L23/528 , G03F1/36 , H01L23/522 , G06F17/50 , H01L27/118 , H01L21/8238 , H01L23/485
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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公开(公告)号：US12062345B2
公开(公告)日：2024-08-13
申请号：US17982165
申请日：2022-11-07
发明人： Seungyong Shin , Kyehoon Lee , Sungyeol Kim , Jonghoon Jung
IPC分类号： G09G3/36
CPC分类号： G09G3/3607 , G09G2310/08 , G09G2320/0233 , G09G2320/0271
摘要： A display device, which fixes the magnitude of a driving current flowing through light-emitting devices in a low luminance region and controls an application period of the driving current, includes: light-emitting devices; a processor for controlling the light-emitting devices on the basis of a gray level required for the light-emitting devices in each unit frame; and a timing controller which divides the unit frame into a plurality of sub-frames and generates a scan signal corresponding to each sub-frame. The processor: when the gray level is greater than or equal to a preset value, determines a luminance value of the light-emitting devices on the basis of the gray level and turns on the light-emitting devices with the determined luminance value in all of the plurality of sub-frames; when the gray level is less than the preset value, determines a light-emitting period of the light-emitting devices on the basis of the gray level and divides, on the basis of the light-emitting period, the plurality of sub-frames into a first and a second sub-frame group; turns on the light-emitting devices with a preset luminance value in all sub-frames belonging to the first sub-frame group; and turns off the light-emitting devices in sub-frames belonging to the second sub-frame group or turns on the light-emitting devices with a luminance value less than the preset luminance value.
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公开(公告)号：US11323119B2
公开(公告)日：2022-05-03
申请号：US17088819
申请日：2020-11-04
发明人： Taejoong Song , Jungho Do , Seungyoung Lee , Jonghoon Jung
IPC分类号： H03K19/17724 , H01L27/02 , H01L29/06 , H01L23/528 , H01L29/423 , H01L27/088
摘要： A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.
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公开(公告)号：US10217647B2
公开(公告)日：2019-02-26
申请号：US16032127
申请日：2018-07-11
发明人： Jung-Ho Do , Jonghoon Jung , Sanghoon Baek , Seungyoung Lee , Taejoong Song , Jinyoung Lim
IPC分类号： H01L21/8238 , H01L21/3213
摘要： A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.
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公开(公告)号：US20230384636A1
公开(公告)日：2023-11-30
申请号：US18118979
申请日：2023-03-08
发明人： Chunsoon Park , Sungyeol Kim , Seungyong Shin , Jonghoon Jung
IPC分类号： G02F1/13357 , G02F1/1335 , H01L25/075 , H01L33/62
CPC分类号： G02F1/133603 , G02F1/133612 , H01L25/0753 , H01L33/62 , G02F2201/50
摘要： Provided is a display apparatus having an improved degree of freedom in wiring design, the display apparatus including: a liquid crystal panel; and a light source apparatus, wherein the light source apparatus includes: a substrate; and a plurality of light emitting diodes (LEDs) provided on the substrate, wherein each of the plurality of LEDs has a lower surface in contact with a first feeding pad and a second feeding pad formed on the substrate, the lower surface of each of the plurality of LEDs includes a first contact area provided to be in contact with the first feeding pad, a second contact area provided to be in contact with the second feeding pad, and a non-contact area other than the first contact area and the second contact area on the lower surface, and each of the first contact area and the second contact area is smaller than the non-contact area.
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公开(公告)号：US11830453B2
公开(公告)日：2023-11-28
申请号：US17742992
申请日：2022-05-12
发明人： Jonghoon Jung , Sungyeol Kim , Seungyong Shin , Junsung Choi
CPC分类号： G09G3/3648 , G09G3/3426 , G09G2320/0233 , G09G2330/021
摘要： A display apparatus includes a liquid crystal panel, a power supply, a backlight unit including a plurality of sub-blocks configured to radiate light to the liquid crystal panel, and a controller configured to determine a peak voltage and a source voltage supplied to each of the plurality of sub-blocks. Each of the plurality of sub-blocks includes a first switching element configured to receive the peak voltage as a gate voltage, and a second switching element including a drain terminal connected to a source terminal of the first switching element, the second switching element configured to receive an amount of charges corresponding to the source voltage through a gate terminal.
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公开(公告)号：US10916535B2
公开(公告)日：2021-02-09
申请号：US16727280
申请日：2019-12-26
发明人： Jung-Ho Do , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L23/528 , G03F1/36 , H01L23/522 , H01L27/118 , H01L21/8238 , H01L23/485 , H01L27/092 , G06F30/398 , G06F119/18
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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公开(公告)号：US10541243B2
公开(公告)日：2020-01-21
申请号：US15355159
申请日：2016-11-18
发明人： Jung-Ho Do , Seungyoung Lee , Jonghoon Jung , Jinyoung Lim , Giyoung Yang , Sanghoon Baek , Taejoong Song
IPC分类号： H01L27/11 , H01L23/522 , H01L23/485
摘要： A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.
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公开(公告)号：US20180350791A1
公开(公告)日：2018-12-06
申请号：US15870143
申请日：2018-01-12
发明人： Jung-Ho Do , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L27/092 , H01L23/522 , H01L23/528 , G06F17/50 , G03F1/36
CPC分类号： H01L27/0207 , G03F1/36 , G06F17/5081 , G06F2217/12 , H01L21/823871 , H01L21/823878 , H01L23/485 , H01L23/5223 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L27/092 , H01L27/11807 , H01L2027/11875 , H01L2027/11881
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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