公开(公告)号：US20200027734A1

公开(公告)日：2020-01-23

申请号：US16460468

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-jung KIM ,  Kiseok LEE ,  Keunnam KIM ,  Yoosang HWANG

IPC: H01L21/02 ,  H01L21/306 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate, forming a hole penetrating the mold structure, forming on the substrate a second semiconductor layer filling the hole, and irradiating a laser onto the second semiconductor layer.

公开(公告)号：US20220102352A1

公开(公告)日：2022-03-31

申请号：US17241860

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Kyunghwan LEE ,  Dongoh KIM ,  Yongseok KIM ,  Hui-jung KIM ,  Min Hee CHO

IPC: H01L27/108

Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

公开(公告)号：US20200035541A1

公开(公告)日：2020-01-30

申请号：US16258815

申请日：2019-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-hwan Chun ,  Hui-jung KIM ,  Keun-nam KIM ,  Sung-hee HAN ,  Yoo-sang HWANG

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06 ,  H01L27/108

Abstract: A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.

公开(公告)号：US20190189617A1

公开(公告)日：2019-06-20

申请号：US16014118

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-jung KIM ,  Sung-hee Han ,  Ki-seok Lee ,  Bong-soo Kim ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/91

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.