公开(公告)号：US10468350B2

公开(公告)日：2019-11-05

申请号：US15592860

申请日：2017-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US20190097007A1

公开(公告)日：2019-03-28

申请号：US15914611

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-hyeok AHN ,  Eun-jung Kim ,  Hui-jung Kim ,  Ki-seok Lee ,  Bong-soo Kim ,  Myeong-dong Lee ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/762 ,  H01L21/74

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

公开(公告)号：US10896966B2

公开(公告)日：2021-01-19

申请号：US16385245

申请日：2019-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-jin Lee ,  Bong-soo Kim ,  Ji-young Kim ,  Ho-rim Yoo

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate including a first region and a second region, a buried gate structure located on a first recess in the first region of the substrate, and a recess gate structure located on a second recess in the second region of the substrate, wherein the buried gate structure is buried in the substrate, an upper portion of the recess gate structure is not buried in the substrate, and a first work function adjustment layer in the buried gate structure may include a material identical to a material included in a second work function layer of the recess gate structure.

公开(公告)号：US20190027482A1

公开(公告)日：2019-01-24

申请号：US15986064

申请日：2018-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGWOO KIM ,  Bong-soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24

CPC classification number: H01L27/10897 ,  G11C11/005 ,  G11C14/0045 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.

公开(公告)号：US20180040560A1

公开(公告)日：2018-02-08

申请号：US15592860

申请日：2017-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/2436 ,  H01L27/2463

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US11776909B2

公开(公告)日：2023-10-03

申请号：US17205462

申请日：2021-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L21/764 ,  H01L23/532 ,  H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/0335 ,  H01L23/5222 ,  H10B12/315 ,  H10B63/30 ,  H10B63/80

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US20210210432A1

公开(公告)日：2021-07-08

申请号：US17205462

申请日：2021-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US20190189617A1

公开(公告)日：2019-06-20

申请号：US16014118

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-jung KIM ,  Sung-hee Han ,  Ki-seok Lee ,  Bong-soo Kim ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/91

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

公开(公告)号：US20190074381A1

公开(公告)日：2019-03-07

申请号：US16120726

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/86 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A device including a two-dimensional (2D) material includes a substrate including a recess recessed from a main surface of the substrate and extending in a first direction, a 2D material pattern on the substrate and intersecting with the recess of the substrate, a gate structure contacting the 2D material pattern and extending in the first direction along the recess of the substrate, a first electrode contacting a first end of the 2D material pattern, and a second electrode contacting a second end of the 2D material pattern. The 2D material pattern extends in a second direction and includes atomic layers that are parallel to a surface of the substrate.

公开(公告)号：US20190074380A1

公开(公告)日：2019-03-07

申请号：US16120705

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin PARK ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/86 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.