公开(公告)号：US10777276B2

公开(公告)日：2020-09-15

申请号：US16533143

申请日：2019-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-woo Kim ,  Jae-kyu Lee ,  Ki-seok Suh ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Gwan-hyeob Koh

IPC: H01L23/528 ,  G11C14/00 ,  H01L45/00 ,  H01L29/08 ,  H01L27/108 ,  H01L29/423 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L27/24 ,  H01L27/22 ,  H01L27/105 ,  H01L27/02 ,  G11C7/10 ,  G11C11/00

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

公开(公告)号：US09548260B2

公开(公告)日：2017-01-17

申请号：US14175305

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Park ,  Dae-ik Kim ,  Ji-young Kim ,  Nak-jin Son ,  Yoo-sang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/485 ,  H01L27/108 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.

Abstract translation: 半导体器件包括具有目标连接区域的衬底; 导电线，其具有通过至少绝缘层与衬底间隔开的第一侧壁和将导电线电连接到目标连接区域的导电插塞结构，其中导电插塞包括第一导电插塞，第一导电插塞具有第一侧壁 ，与基板的目标连接区域接触的底表面和面对导电线的第一侧壁的第二侧壁，以及在导线和第一导电塞之间的第二导电塞。 第二导电插头接触导电线的第一侧壁和第一导电插塞的第二侧壁。

公开(公告)号：US08785998B2

公开(公告)日：2014-07-22

申请号：US13724799

申请日：2012-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-woo Chung ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Dae-ik Kim

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

Abstract translation: 半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向 ，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上， 所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向 以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。

公开(公告)号：US20190097007A1

公开(公告)日：2019-03-28

申请号：US15914611

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-hyeok AHN ,  Eun-jung Kim ,  Hui-jung Kim ,  Ki-seok Lee ,  Bong-soo Kim ,  Myeong-dong Lee ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/762 ,  H01L21/74

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

公开(公告)号：US09754944B2

公开(公告)日：2017-09-05

申请号：US14539558

申请日：2014-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Yoo-sang Hwang

IPC: H01L21/768 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.

公开(公告)号：US11152369B2

公开(公告)日：2021-10-19

申请号：US16851957

申请日：2020-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Sung-hee Han ,  Ki-seok Lee ,  Bong-Soo Kim ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L49/02

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

公开(公告)号：US10886167B2

公开(公告)日：2021-01-05

申请号：US16258815

申请日：2019-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-hwan Chun ,  Hui-jung Kim ,  Keun-nam Kim ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06 ,  H01L27/108

Abstract: A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.

公开(公告)号：US10510759B2

公开(公告)日：2019-12-17

申请号：US16004937

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-jung Kim ,  Bong-soo Kim ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L21/768 ,  H01L49/02 ,  H01L21/321 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.

公开(公告)号：US10128252B2

公开(公告)日：2018-11-13

申请号：US15646540

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok Lee ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Bong-soo Kim ,  Je-min Park

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/167 ,  H01L29/36 ,  G11C11/4091 ,  G11C11/408 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

公开(公告)号：US20180175045A1

公开(公告)日：2018-06-21

申请号：US15646540

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok LEE ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Bong-soo Kim ,  Je-min Park

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/167 ,  H01L29/36 ,  G11C11/4091 ,  G11C11/408

CPC classification number: H01L27/10897 ,  G11C11/4085 ,  G11C11/4091 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42376

Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.