公开(公告)号：US20250125217A1

公开(公告)日：2025-04-17

申请号：US18652490

申请日：2024-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol KIM ,  Hyoeun KIM ,  Huiyeong JANG

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L29/04 ,  H01L29/36

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a second semiconductor chip on a top surface of the first semiconductor chip and having a width less than that of the first semiconductor chip, and a molding layer on the first semiconductor chip and surrounding the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate. The first semiconductor substrate includes a first part adjacent to the top surface of the first semiconductor substrate and a second part adjacent to a bottom surface of the first semiconductor substrate. The first and second parts include the same semiconductor material. The first part has a single crystalline structure. The second part may have a polycrystalline structure.

公开(公告)号：US20240096841A1

公开(公告)日：2024-03-21

申请号：US18456261

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk KWON ,  Sunjae KIM ,  Seunghoon YEON ,  Seungryong OH ,  Huiyeong JANG

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L22/32 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/3841

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of through electrodes penetrating the first substrate, and first bonding pads provided on one surface of the first substrate and electrically connected to the plurality of through electrodes, a second semiconductor chip including a second substrate, a second wiring layer provided on one surface of the second substrate and having redistribution pads and test pads, and second bonding pads on the redistribution pads, the second semiconductor chip being stacked on the first semiconductor chip via conductive bumps that are disposed between first and second bonding pads, an adhesive layer filling a space between the conductive bumps, and flow prevention structures in the adhesive layer on a test pad region where the test pads are disposed.