公开(公告)号：US20200098918A1

公开(公告)日：2020-03-26

申请号：US16693439

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jong LEE ,  Sanghyuk HONG ,  TaeYong KWON ,  Sunjung KIM ,  Cheol KIM

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

公开(公告)号：US20190080762A1

公开(公告)日：2019-03-14

申请号：US15979669

申请日：2018-05-15

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

Inventor： Cheol KIM ,  HYUN-SUK KANG ,  KEE-WON KWON ,  RAK-JOO SUNG ,  SUNG-GI AHN

IPC: G11C15/04

Abstract: A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.

公开(公告)号：US20170103916A1

公开(公告)日：2017-04-13

申请号：US15182024

申请日：2016-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Ho JEON ,  Sang-Su KIM ,  Cheol KIM ,  Yong-Suk TAK ,  Myung-Geun SONG ,  Gi-Gwan PARK

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/49 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

公开(公告)号：US20190074211A1

公开(公告)日：2019-03-07

申请号：US15962059

申请日：2018-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Seok MIN ,  Dong Kwon KIM ,  Cheol KIM ,  Young Mook OH ,  Jeong Yun LEE ,  Hyun Ho JUNG

IPC: H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having an active pattern extending in a first direction, a first gate structure and a second gate structure extending in a second direction, intersecting the first direction, to traverse the active pattern, the first gate structure and the second gate structure isolated from each other while facing each other in the second direction, a gate isolation pattern disposed between the first gate structure and the second gate structure, the gate isolation pattern having a void, and a filling insulating portion positioned lower than upper surfaces of the first gate structure and the second gate structure within the gate isolation pattern, the filling insulating portion being connected to at least an upper end of the void.

公开(公告)号：US20160079125A1

公开(公告)日：2016-03-17

申请号：US14812137

申请日：2015-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min KIM ,  Cheol KIM ,  Dong-Ho CHA

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: In a method of manufacturing a semiconductor device, a substrate is etched to form active fins spaced apart from one another in a first direction, and each active fin extends in the first direction. An isolation pattern is formed on the substrate to partially fill a space between the active fins. A mold pattern is formed on the isolation pattern, the mold pattern covering at least a portion of each of the active fins and including an opening exposing a portion of the isolation pattern between the active fins in the first direction. An insulation pattern is formed to fill the opening. The mold pattern is removed to expose the active fins. A gate structure and a dummy structure are formed on the exposed active fins and the insulation pattern, respectively, the gate structure and the dummy structure extending in a second direction substantially perpendicular to the first direction.

Abstract translation: 在制造半导体器件的方法中，蚀刻衬底以形成在第一方向上彼此间隔开的有效散热片，并且每个活动鳍片沿第一方向延伸。 在衬底上形成隔离图案，以部分填充活性鳍片之间的空间。 在隔离图案上形成模具图案，模具图案覆盖每个活动翅片的至少一部分，并且包括在第一方向上暴露活动翅片之间的隔离图案的一部分的开口。 形成绝缘图案以填充开口。 去除模具图案以暴露活性散热片。 分别在暴露的活性鳍片和绝缘图案上形成栅极结构和虚拟结构，栅极结构和虚拟结构在基本上垂直于第一方向的第二方向上延伸。

公开(公告)号：US20130322160A1

公开(公告)日：2013-12-05

申请号：US13799967

申请日：2013-03-13

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Cheol KIM ,  Sang-ho SHIN ,  Jung-sik KIM

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C29/4401 ,  G11C29/783 ,  G11C29/785 ,  G11C29/787 ,  G11C2029/4402

Abstract: A memory device to correct a defect cell generated after packing is performed includes a memory cell array in which a plurality of memory cells are arranged, a repair circuit unit including a first storage unit to store defect cell information in the memory cell array, and a fuse circuit unit including a second storage unit that is programmed according to the defect cell information stored in the first storage unit. The first storage unit includes a volatile memory device, and the second storage unit includes a non-volatile memory device.

Abstract translation: 用于校正打包后产生的缺陷单元的存储装置包括其中布置多个存储单元的存储单元阵列，包括存储单元阵列中的缺陷单元信息的第一存储单元的修复电路单元，以及 熔丝电路单元，包括根据存储在第一存储单元中的缺陷单元信息编程的第二存储单元。 第一存储单元包括易失性存储器件，并且第二存储单元包括非易失性存储器件。

公开(公告)号：US20250126854A1

公开(公告)日：2025-04-17

申请号：US18989332

申请日：2024-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyun PARK ,  Kye-hyun BAEK ,  Yong-ho JEON ,  Cheol KIM ,  Sung-il PARK ,  Yun-il LEE ,  Hyung-suk LEE

IPC: H10D62/10 ,  H10D30/01 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

公开(公告)号：US20250125217A1

公开(公告)日：2025-04-17

申请号：US18652490

申请日：2024-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol KIM ,  Hyoeun KIM ,  Huiyeong JANG

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L29/04 ,  H01L29/36

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a second semiconductor chip on a top surface of the first semiconductor chip and having a width less than that of the first semiconductor chip, and a molding layer on the first semiconductor chip and surrounding the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate. The first semiconductor substrate includes a first part adjacent to the top surface of the first semiconductor substrate and a second part adjacent to a bottom surface of the first semiconductor substrate. The first and second parts include the same semiconductor material. The first part has a single crystalline structure. The second part may have a polycrystalline structure.

公开(公告)号：US20220344461A1

公开(公告)日：2022-10-27

申请号：US17516192

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae Geon JUNG ,  Dong Kwon KIM ,  Cheol KIM

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a first active pattern that includes a first side wall and a second side wall opposite to the first side wall in a second horizontal direction, a first insulating structure in a first trench extending in the first horizontal direction on the first side wall of the first active pattern, a second insulating structure in a second trench extending in the first horizontal direction on the second side of the first active pattern, and includes a first insulating layer on side walls and a bottom surface of the second trench, and a second insulating layer in the second trench on the first insulating layer, a gate-cut extending in the first horizontal direction on the first insulating structure, and a gate electrode extending in the second horizontal direction on the first active pattern.

公开(公告)号：US20190013401A1

公开(公告)日：2019-01-10

申请号：US16128152

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Kyung-Seok OH ,  Cheol KIM ,  Heon-Jong SHIN ,  Jong-Ryeol YOO ,  Hyun-Jung LEE ,  Seong-Hoon JEONG

IPC: H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.