公开(公告)号：US20240055421A1

公开(公告)日：2024-02-15

申请号：US18320013

申请日：2023-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Yun KWEON ,  Yeong Beom KO ,  Woo Ju KIM ,  Jung Seok RYU ,  Hwa Young LEE ,  Hyun Su HWANG

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L25/0652 ,  H01L24/08 ,  H01L23/5386 ,  H01L23/5384 ,  H01L23/3121 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/181 ,  H01L2224/081 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A method for manufacturing semiconductor device includes preparing a semiconductor wafer including a first semiconductor substrate and a first through silicon via; removing a trim region of the first semiconductor substrate along an edge portion of the semiconductor wafer to form a remaining edge region; attaching the semiconductor wafer to a carrier substrate, wherein the remaining edge region is in contact with the carrier substrate; forming an edge protection layer along the remaining edge region; exposing the first through silicon via by removing a predetermined depth of the first semiconductor substrate; forming a second final passivation layer to expose the upper surface of the first through silicon via; forming a plurality of first upper connection pads on the second final passivation layer; and dicing the semiconductor wafer into a plurality of first semiconductor chips.