公开(公告)号：US20240170440A1

公开(公告)日：2024-05-23

申请号：US18373405

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanyoung CHOI ,  Seokhyun LEE ,  Seokgeun AHN

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/33 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/3303 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/2064

Abstract: A semiconductor package includes first semiconductor chips electrically connected to each other through a through-via electrically connecting a first front surface pad and a first rear surface pad. A second semiconductor chip has a second lower surface including a second front surface pad, a second upper surface, a second side surface extending from the second upper surface, and a recess surface extending from the second lower surface to the second side surface. First adhesive films are on a first lower surface of first semiconductor chips and include first extension portions extending further outwardly than a first side surface of the first semiconductor chips. A second adhesive film is on the second lower surface and includes a second extension portion extending further outwardly than the second side surface. In a horizontal direction, a length of the second extension portion is less than a length of each of the first extension portions.

公开(公告)号：US20210398947A1

公开(公告)日：2021-12-23

申请号：US17352757

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Insup SHIN ,  Hyeongmun KANG ,  Jungmin KO ,  Hwanyoung CHOI

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.