公开(公告)号：US20240347407A1

公开(公告)日：2024-10-17

申请号：US18753139

申请日：2024-06-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chen LAI ,  Ming-Chih YEW ,  Po-Yao LIN ,  Chin-Hua WANG ,  Shin-Puu JENG

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/3185 ,  H01L21/565 ,  H01L23/145 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/35121

摘要： Structures and formation methods of a chip package structure are provided. The method includes mounting semiconductor dies over die regions of an interposer substrate. The adjacent die regions are separated from one another by a gap region of the interposer substrate. The method also includes forming first underfill material layers and a second gap-filling layer over the interposer substrate corresponding to the gap region. The method further includes forming an encapsulating layer over the interposer substrate to surround the semiconductor dies, the first underfill material layers, and the second underfill material layer. The gap region has ends and the first underfill material layers is formed adjacent to the ends of the gap region. The Young's modulus of the second underfill material layer is less than that of the first underfill material layers.

公开(公告)号：US20240282713A1

公开(公告)日：2024-08-22

申请号：US18173027

申请日：2023-02-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hsuan Tsai ,  Yu-Lin CHIANG ,  Chin-Chuan Chang ,  Ying-Ching Shih

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC分类号： H01L23/5386 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/0801 ,  H01L2224/08058 ,  H01L2224/08059 ,  H01L2224/0807 ,  H01L2224/08235 ,  H01L2224/08238 ,  H01L2224/16235 ,  H01L2224/3201 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186

摘要： A package structure includes a first redistribution circuit structure, a first semiconductor die, and a second semiconductor die. The first redistribution circuit structure has a first side and a second side opposite to the first side. The first semiconductor die is disposed over the firs side of the first redistribution circuit structure. The second semiconductor die is disposed over the second side of the first redistribution circuit structure and is electrically connected thereto, where the second semiconductor die includes a substrate, an interconnect structure disposed on the substrate, a plurality of conductive terminals disposed on and electrically connected to the interconnect structure, and a dielectric layer disposed on the interconnect structure and laterally covering the plurality of conductive terminals. A material of the dielectric layer included in the second semiconductor die is different from a material of a dielectric layer included in the first redistribution circuit structure.

公开(公告)号：US12062633B2

公开(公告)日：2024-08-13

申请号：US17551387

申请日：2021-12-15

申请人： Samsung Electronics Co., Ltd.

发明人： Joungphil Lee ,  Yeongseok Kim

IPC分类号： H01L23/00 ,  C08K3/013 ,  C08K5/00 ,  C08L63/00 ,  H01L21/66 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L24/29 ,  C08K3/013 ,  C08K5/0041 ,  C08L63/00 ,  H01L22/30 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/27515 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33055 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/16251 ,  H01L2924/182

摘要： Provided is a semiconductor package including: at least one semiconductor device on a first substrate; a non-conductive film (NCF) on the at least one semiconductor device and comprising an irreversible thermochromic pigment; and a molding member on the at least one semiconductor device in a lateral direction, wherein a content of the irreversible thermochromic pigment in the NCF is about 0.1 wt % to about 5 wt % with respect to a weight of the NCF.

公开(公告)号：US12015007B2

公开(公告)日：2024-06-18

申请号：US18074671

申请日：2022-12-05

申请人： Samsung Display Co., LTD.

发明人： Hong Am Kim ,  Young Min Cho

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/73 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/17515 ,  H01L2224/29078 ,  H01L2224/29083 ,  H01L2224/29193 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06596

摘要： A display device includes a substrate including a conductive pad, a driving chip facing the substrate and including a conductive bump electrically connected to the conductive pad and an inspection bump which is insulated from the conductive pad, and an adhesive member which is between the conductive pad and the driving chip and connects the conductive pad to the driving chip. The adhesive member includes a first adhesive layer including a conductive ball, and a second adhesive layer facing the first adhesive layer, the second adhesive layer including a first area including a color-changing material, and a second area adjacent to the first area and excluding the color-changing material.

公开(公告)号：US20240178082A1

公开(公告)日：2024-05-30

申请号：US18071797

申请日：2022-11-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WU-DER YANG

IPC分类号： H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/13 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/3201 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32235 ,  H01L2224/3303 ,  H01L2224/33051 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/2027

摘要： A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.

公开(公告)号：US11955449B2

公开(公告)日：2024-04-09

申请号：US18054530

申请日：2022-11-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/32 ,  H01L24/03 ,  H01L24/08 ,  H01L24/27 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0346 ,  H01L2224/08146 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586

摘要： A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

公开(公告)号：US20240096648A1

公开(公告)日：2024-03-21

申请号：US18509801

申请日：2023-11-15

申请人： Apple Inc.

发明人： Sanjay Dabral ,  Chi Nung Ni ,  Long Huang ,  SivaChandra Jangam

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L21/56 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/32059 ,  H01L2224/32137 ,  H01L2924/183

摘要： Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.

公开(公告)号：US20240030176A1

公开(公告)日：2024-01-25

申请号：US18112323

申请日：2023-02-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ji-Yong PARK ,  Jeong Hyun Lee ,  Choon Bin Yim

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/13

CPC分类号： H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L21/565 ,  H01L21/561 ,  H01L21/4853 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/13 ,  H01L24/83 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/3201 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1011 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/29005 ,  H01L2224/83091 ,  H01L2224/83201

摘要： A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.

公开(公告)号：US20230317539A1

公开(公告)日：2023-10-05

申请号：US17986995

申请日：2022-11-15

申请人： Samsung Electronics Co., Ltd.

发明人： Bo In NOH ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/3135 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L23/315 ,  H01L23/49822 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/3511 ,  H01L2224/73204 ,  H01L2224/16014 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/186 ,  H01L2224/3201 ,  H01L2224/32055 ,  H01L2224/32053 ,  H01L2224/32059 ,  H01L23/49816 ,  H01L25/0655

摘要： A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

公开(公告)号：US11688712B2

公开(公告)日：2023-06-27

申请号：US16792682

申请日：2020-02-17

申请人： Infineon Technologies AG

发明人： Olaf Hohlfeld

IPC分类号： H01L23/00 ,  H01L27/12

CPC分类号： H01L24/34 ,  H01L27/1248 ,  H01L2224/32013 ,  H01L2224/32054 ,  H01L2224/32055 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32113 ,  H01L2224/32258 ,  H01L2224/49175

摘要： A semiconductor arrangement includes a semiconductor substrate having a dielectric insulation layer and at least a first metallization layer arranged on a first side of the dielectric insulation layer. The first metallization layer includes at least two sections, each section being separated from a neighboring section by a recess. A semiconductor body is arranged on one of the sections of the first metallization layer. At least one indentation is arranged between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.