DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

    公开(公告)号:US20210006254A1

    公开(公告)日:2021-01-07

    申请号:US16800038

    申请日:2020-02-25

    Abstract: A delay locked loop circuit including: a clock signal input buffer to buffer an input clock signal and generate a reference clock signal; a delay unit to delay the reference clock signal in response to a coarse and fine delay code and generate an internal clock signal; a clock signal delay replica unit to delay the internal clock signal and generate a feedback clock signal; a coarse delay control unit to receive the reference and feedback clock signals, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal occurring before the transition time point of the reference clock signal, and generate a coarse delay code; and a fine delay control unit to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate a fine delay code.

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