公开(公告)号：US20250107185A1

公开(公告)日：2025-03-27

申请号：US18738197

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyohoon BYEON ,  Seokhoon Kim ,  Pankwi Park ,  Sungkeun Lim ,  Yuyeong Jo

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, a gate electrode on the plurality of semiconductor patterns, and extending in a first horizontal direction, a gate spacer disposed on a sidewall of the gate electrode in a second horizontal direction crossing the first horizontal direction, a source/drain pattern electrically connected to the plurality of semiconductor patterns, and including a first epitaxial pattern and a second epitaxial pattern on a side surface of the first epitaxial pattern in the second horizontal direction, and a protection pattern between at least one of the plurality of semiconductor patterns and the gate spacer and including a material having an etch selectivity with the first epitaxial pattern.

公开(公告)号：US20240021734A1

公开(公告)日：2024-01-18

申请号：US18121869

申请日：2023-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyohoon BYEON ,  SUNGKEUN LIM ,  YUYEONG JO ,  JINYEONG JOE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392 ,  H01L27/092

Abstract: A semiconductor device and a fabrication method thereof are disclosed. The device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of vertically-stacked semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, the gate electrode including a first portion interposed between first and second semiconductor patterns, which are two adjacent ones of the semiconductor patterns, and a gate insulating layer interposed between the first portion of the gate electrode and the first and second semiconductor patterns. The second semiconductor pattern is located at a tier higher than the first semiconductor pattern. The first semiconductor pattern includes a first channel recess having a first depth, and the second semiconductor pattern includes a second channel recess having a second depth smaller than the first depth.

公开(公告)号：US20240243188A1

公开(公告)日：2024-07-18

申请号：US18513759

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyohoon BYEON ,  Seokhoon KIM ,  Unki KIM ,  Pankwi PARK ,  Sungkeun LIM ,  Yuyeong JO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes: a rear wiring structure; an insulating substrate including fin structures disposed on the rear wiring structure and extending in a first horizontal direction; a device isolation layer disposed between the fin structures; a lower insulating layer covering the fin structures; gate structures extending in a second horizontal direction crossing the first horizontal direction; a plurality of nanosheet stacks disposed on the lower insulating layer; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and through some of the fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.