公开(公告)号：US20230395523A1

公开(公告)日：2023-12-07

申请号：US18234914

申请日：2023-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon PARK ,  Young Min LEE ,  Dae-Woo KIM ,  Hyuek Jae LEE

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L23/5386 ,  H01L23/5385

Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

公开(公告)号：US20210335680A1

公开(公告)日：2021-10-28

申请号：US17367903

申请日：2021-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae LEE ,  Tae Hun Kim ,  Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong

IPC: H01L21/66 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

公开(公告)号：US20220068829A1

公开(公告)日：2022-03-03

申请号：US17199703

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon PARK ,  Young Min LEE ,  Dae-Woo KIM ,  Hyuek Jae LEE

IPC: H01L23/544 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

公开(公告)号：US20220028837A1

公开(公告)日：2022-01-27

申请号：US17493975

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwan HWANG ,  Ji Hoon KIM ,  Ji Seok HONG ,  Tae Hun KIM ,  Hyuek Jae LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.