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    SEMICONDUCTOR PACKAGE
    1.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240030214A1

    公开(公告)日：2024-01-25

    申请号：US18480310

    申请日：2023-10-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Cheon PARK ,  Dae-Woo Kim ,  Taehun Kim ,  Hyuekjae Lee

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

    CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49822

    Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20250079393A1

    公开(公告)日：2025-03-06

    申请号：US18748354

    申请日：2024-06-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Cheon PARK ,  Un-Byoung KANG ,  Ku Young KIM ,  Jun Woo MYUNG ,  Seung-Jin LEE ,  Ji-Seok HONG

    IPC: H01L23/00 ,  H01L23/28 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

    Abstract: A semiconductor package includes: a first semiconductor chip including a first substrate and a first through electrode passing through the first substrate, wherein the first substrate has a first active surface and a first non-active surface; a chip structure including a plurality of second semiconductor chips stacked on the first semiconductor chip, wherein each second semiconductor chip includes a second substrate and a second through electrode passing through the second substrate; and a third semiconductor chip disposed on the chip structure, and including a third substrate, wherein the first substrate has a first width and a first thickness, wherein the second substrate has a second width and a second thickness, and the third substrate has a third width and a third thickness, wherein the third thickness is thicker than the second thickness, and the third width is greater than the second width.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20240413104A1

    公开(公告)日：2024-12-12

    申请号：US18425173

    申请日：2024-01-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang Cheon PARK ,  Ji-Seok HONG ,  Un-Byoung KANG ,  Ku Young KIM

    IPC: H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B80/00

    Abstract: There is provided a semiconductor device with improved product reliability. The semiconductor device includes a substrate, a structure on the substrate and including multilayer metal patterns and multilayer insulating layers, and a pad layer on the structure and including a plurality of bonding pads, wherein a plurality of uppermost patterns at an uppermost layer among the multilayer metal patterns include electrode patterns for transferring signals and alleviation patterns that do not transfer the signals, a first ratio of the alleviation patterns within a first reference shape at a first distance from an edge of the structure is greater than a second ratio of the alleviation patterns within a second reference shape at a second distance from the edge of the structure, and the first distance is greater than the second distance.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220068829A1

    公开(公告)日：2022-03-03

    申请号：US17199703

    申请日：2021-03-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang Cheon PARK ,  Young Min LEE ,  Dae-Woo KIM ,  Hyuek Jae LEE

    IPC: H01L23/544 ,  H01L23/538 ,  H01L25/065

    Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

    SEMICONDUCTOR PACKAGE
    7.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20230395523A1

    公开(公告)日：2023-12-07

    申请号：US18234914

    申请日：2023-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang Cheon PARK ,  Young Min LEE ,  Dae-Woo KIM ,  Hyuek Jae LEE

    IPC: H01L23/544 ,  H01L25/065 ,  H01L23/538

    CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L23/5386 ,  H01L23/5385

    Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220165722A1

    公开(公告)日：2022-05-26

    申请号：US17381985

    申请日：2021-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Cheon PARK ,  Dae-Woo Kim ,  Taehun Kim ,  Hyuekjae Lee

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

    Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

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