公开(公告)号：US20240203939A1

公开(公告)日：2024-06-20

申请号：US18219394

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Dae-Woo KIM ,  Won-Young KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L24/32 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/80001

Abstract: A semiconductor package includes a power delivery network, a semiconductor chip on a top surface of the power delivery network, and having first and second surfaces opposite to each other, a second semiconductor chip on the top surface horizontally spaced from the first semiconductor chip, the second semiconductor chip having third surface and fourth surfaces, opposite to each other, chip stacks on the first semiconductor chip, and on the second semiconductor chip. The first surface is an active surface. The third surface is an active surface of the second semiconductor chip. The first chip stack includes third semiconductor chips on the first surface of the first semiconductor chip. The third semiconductor chips is disposed such that an active surface thereof faces the first semiconductor chip, and the first chip stack and the second semiconductor chip may be electrically connected to each other through the power delivery network.

公开(公告)号：US20240222230A1

公开(公告)日：2024-07-04

申请号：US18353313

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo CHUNG ,  Dae-Woo KIM ,  Young Lyong KIM ,  Inhyo HWANG

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/29 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L23/293 ,  H01L23/5384

Abstract: A semiconductor package according to at least one embodiment may include: a first chiplet and a second chiplet disposed side by side with each other, wherein each of the first chiplet and the second comprises a substrate including an active side and a back side opposite to the active side; a back side power distribution network (BSPDN) in the back side of the substrate; and a third chiplet electrically coupling the first chiplet and the second chiplet to each other above the first chiplet and the second chiplet; and a fourth chiplet and a fifth chiplet disposed side by side with the third chiplet.

公开(公告)号：US20220068829A1

公开(公告)日：2022-03-03

申请号：US17199703

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon PARK ,  Young Min LEE ,  Dae-Woo KIM ,  Hyuek Jae LEE

IPC: H01L23/544 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

公开(公告)号：US20230395523A1

公开(公告)日：2023-12-07

申请号：US18234914

申请日：2023-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon PARK ,  Young Min LEE ,  Dae-Woo KIM ,  Hyuek Jae LEE

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L23/5386 ,  H01L23/5385

Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.