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公开(公告)号:US09960182B2
公开(公告)日:2018-05-01
申请号:US15634555
申请日:2017-06-27
发明人: Ji-Hoon Choi , SeungHyun Lim , Sunggil Kim , HongSuk Kim , Hunhyeong Lim , Hyunjun Sim
IPC分类号: H01L27/115 , H01L29/10 , H01L27/11582 , H01L27/11565 , H01L27/1157
CPC分类号: H01L27/11582 , H01L27/11565 , H01L27/1157
摘要: A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.